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[RISCV] Use f64 for LocVT for ilp32 when whole f64 is passed on the stack. NFC #69118

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Merged
merged 2 commits into from
Oct 16, 2023
Merged

[RISCV] Use f64 for LocVT for ilp32 when whole f64 is passed on the stack. NFC #69118

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dcb4ed7
[RISCV] Use f64 for LocVT on RV32 when whole f64 is passed on the sta…
topperc Oct 15, 2023
286f495
!fixup remove stale comment and fold variable into condition.
topperc Oct 16, 2023
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19 changes: 3 additions & 16 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -16452,13 +16452,13 @@ bool RISCV::CC_RISCV(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo,
// stack. LowerCall/LowerFormalArguments/LowerReturn must recognise these
// cases.
Register Reg = State.AllocateReg(ArgGPRs);
LocVT = MVT::i32;
if (!Reg) {
unsigned StackOffset = State.AllocateStack(8, Align(8));
State.addLoc(
CCValAssign::getMem(ValNo, ValVT, StackOffset, LocVT, LocInfo));
return false;
}
LocVT = MVT::i32;
if (!State.AllocateReg(ArgGPRs))
State.AllocateStack(4, Align(4));
State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
Expand Down Expand Up @@ -16777,15 +16777,6 @@ static SDValue unpackF64OnRV32DSoftABI(SelectionDAG &DAG, SDValue Chain,
MachineFrameInfo &MFI = MF.getFrameInfo();
MachineRegisterInfo &RegInfo = MF.getRegInfo();

if (VA.isMemLoc()) {
// f64 is passed on the stack.
int FI =
MFI.CreateFixedObject(8, VA.getLocMemOffset(), /*IsImmutable=*/true);
SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
return DAG.getLoad(MVT::f64, DL, Chain, FIN,
MachinePointerInfo::getFixedStack(MF, FI));
}

assert(VA.isRegLoc() && "Expected register VA assignment");

Register LoVReg = RegInfo.createVirtualRegister(&RISCV::GPRRegClass);
Expand Down Expand Up @@ -17298,9 +17289,8 @@ SDValue RISCVTargetLowering::LowerCall(CallLoweringInfo &CLI,
ISD::ArgFlagsTy Flags = Outs[i].Flags;

// Handle passing f64 on RV32D with a soft float ABI as a special case.
bool IsF64OnRV32DSoftABI =
VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64;
if (IsF64OnRV32DSoftABI && VA.isRegLoc()) {
if (VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64) {
assert(VA.isRegLoc() && "Expected register VA assignment");
SDValue SplitF64 = DAG.getNode(
RISCVISD::SplitF64, DL, DAG.getVTList(MVT::i32, MVT::i32), ArgValue);
SDValue Lo = SplitF64.getValue(0);
Expand All @@ -17326,9 +17316,6 @@ SDValue RISCVTargetLowering::LowerCall(CallLoweringInfo &CLI,
continue;
}

// IsF64OnRV32DSoftABI && VA.isMemLoc() is handled below in the same way
// as any other MemLoc.

// Promote the value if needed.
// For now, only handle fully promoted and indirect arguments.
if (VA.getLocInfo() == CCValAssign::Indirect) {
Expand Down