Skip to content

[PowerPC] Optimize allocation of Conditional Register #69299

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
wants to merge 14 commits into
base: main
Choose a base branch
from
Open

[PowerPC] Optimize allocation of Conditional Register #69299

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
14 commits
Select commit Hold shift + click to select a range
13c0eff
Adjust CR allocation
Oct 17, 2023
c5c7e28
Minor
Oct 17, 2023
8e3f7f6
Update test checks
Oct 18, 2023
57b6171
Add FIXME
Oct 18, 2023
d6ec3aa
Do not skip
Nov 21, 2023
9ec2031
Up
Nov 21, 2023
e755a1f
Clean
Nov 21, 2023
8a0ddf2
Add FIXME
Nov 21, 2023
5c93cb2
Up
Nov 21, 2023
79e232f
Minor
Nov 21, 2023
fccbf7f
Minor
Nov 21, 2023
4a616ed
Tune
Nov 21, 2023
c4ed4fa
Minor
Nov 23, 2023
b6e5b63
Rename
Nov 23, 2023
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
80 changes: 75 additions & 5 deletions llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -76,6 +76,11 @@ MaxCRBitSpillDist("ppc-max-crbit-spill-dist",
"spill on ppc"),
cl::Hidden, cl::init(100));

static cl::opt<unsigned> CRWAWWindowSize(
"ppc-cr-waw-window",
cl::desc("Maximum search distance for definition of CR fields on ppc"),
cl::Hidden, cl::init(3));

// Copies/moves of physical accumulators are expensive operations
// that should be avoided whenever possible. MMA instructions are
// meant to be used in performance-sensitive computational kernels.
Expand Down Expand Up @@ -565,6 +570,8 @@ bool PPCRegisterInfo::getRegAllocationHints(Register VirtReg,
const VirtRegMap *VRM,
const LiveRegMatrix *Matrix) const {
const MachineRegisterInfo *MRI = &MF.getRegInfo();
const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();

// Call the base implementation first to set any hints based on the usual
// heuristics and decide what the return value should be. We want to return
Expand All @@ -582,15 +589,22 @@ bool PPCRegisterInfo::getRegAllocationHints(Register VirtReg,
if (MF.getSubtarget<PPCSubtarget>().isISAFuture())
return BaseImplRetVal;

// We are interested in instructions that copy values to ACC/UACC.
// The copy into UACC will be simply a COPY to a subreg so we
// want to allocate the corresponding physical subreg for the source.
// The copy into ACC will be a BUILD_UACC so we want to allocate
// the same number UACC for the source.
MachineInstr *LastDefMI = nullptr;
bool DefInOneMI = true;
const TargetRegisterClass *RegClass = MRI->getRegClass(VirtReg);
for (MachineInstr &Use : MRI->reg_nodbg_instructions(VirtReg)) {
if (Use.modifiesRegister(VirtReg, TRI)) {
if (LastDefMI)
DefInOneMI = false;
LastDefMI = &Use;
}
const MachineOperand *ResultOp = nullptr;
Register ResultReg;
// We are interested in instructions that copy values to ACC/UACC.
// The copy into UACC will be simply a COPY to a subreg so we
// want to allocate the corresponding physical subreg for the source.
// The copy into ACC will be a BUILD_UACC so we want to allocate
// the same number UACC for the source.
switch (Use.getOpcode()) {
case TargetOpcode::COPY: {
ResultOp = &Use.getOperand(0);
Expand Down Expand Up @@ -628,6 +642,62 @@ bool PPCRegisterInfo::getRegAllocationHints(Register VirtReg,
}
}
}

// In single MBB, allocate different CRs for neighboring definitions can
// improve performance.
if (DefInOneMI && LastDefMI &&
(RegClass->hasSuperClassEq(&PPC::CRRCRegClass) ||
RegClass->hasSuperClassEq(&PPC::CRBITRCRegClass))) {
std::set<MCRegister> NeighboringAllocatedCRs;
auto FindAllocatedCRs = [&](MachineInstr &MI) {
for (MachineOperand &MO : MI.operands()) {
if (!MO.isReg() || !MO.getReg() || !MO.getReg().isVirtual() ||
!MO.isDef())
continue;
const TargetRegisterClass *RC = MRI->getRegClass(MO.getReg());
if (!RC->hasSuperClassEq(&PPC::CRRCRegClass) &&
!RC->hasSuperClassEq(&PPC::CRBITRCRegClass))
continue;
if (VRM->hasPhys(MO.getReg()))
llvm::copy_if(
TRI->superregs_inclusive(VRM->getPhys(MO.getReg())),
std::inserter(NeighboringAllocatedCRs,
NeighboringAllocatedCRs.begin()),
[&](MCPhysReg SR) { return PPC::CRRCRegClass.contains(SR); });
}
};
{
// Search backward.
unsigned ScanDistance = 0;
auto I = ++LastDefMI->getReverseIterator();
for (; I != LastDefMI->getParent()->rend() &&
ScanDistance < CRWAWWindowSize;
++I, ++ScanDistance)
FindAllocatedCRs(*I);
}
{
// Search forward.
unsigned ScanDistance = 0;
auto I = ++LastDefMI->getIterator();
for (;
I != LastDefMI->getParent()->end() && ScanDistance < CRWAWWindowSize;
++I, ++ScanDistance)
FindAllocatedCRs(*I);
}
llvm::copy_if(llvm::make_range(Order.begin(), Order.end()),
std::back_inserter(Hints), [&](MCPhysReg Reg) {
// Be conservative not to use callee saved CRs.
if (TRI->regsOverlap(Reg, PPC::CR2) ||
TRI->regsOverlap(Reg, PPC::CR3) ||
TRI->regsOverlap(Reg, PPC::CR4))
return false;
return llvm::all_of(
TRI->superregs_inclusive(Reg), [&](MCPhysReg SR) {
return !NeighboringAllocatedCRs.count(SR);
});
});
}

return BaseImplRetVal;
}

Expand Down
16 changes: 8 additions & 8 deletions llvm/test/CodeGen/PowerPC/2008-10-28-f128-i32.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -25,14 +25,14 @@ define i64 @__fixunstfdi(ppc_fp128 %a) nounwind readnone {
; CHECK-NEXT: fcmpu 1, 1, 27
; CHECK-NEXT: lwz 3, 384(1)
; CHECK-NEXT: crand 20, 6, 0
; CHECK-NEXT: cror 20, 4, 20
; CHECK-NEXT: cror 24, 4, 20
; CHECK-NEXT: stfd 28, 432(1) # 8-byte Folded Spill
; CHECK-NEXT: stfd 29, 440(1) # 8-byte Folded Spill
; CHECK-NEXT: stfd 30, 448(1) # 8-byte Folded Spill
; CHECK-NEXT: stfd 31, 456(1) # 8-byte Folded Spill
; CHECK-NEXT: stw 4, 404(1)
; CHECK-NEXT: stw 3, 400(1)
; CHECK-NEXT: bc 4, 20, .LBB0_2
; CHECK-NEXT: bc 4, 24, .LBB0_2
; CHECK-NEXT: # %bb.1: # %bb5
; CHECK-NEXT: li 3, 0
; CHECK-NEXT: li 4, 0
Expand Down Expand Up @@ -106,9 +106,9 @@ define i64 @__fixunstfdi(ppc_fp128 %a) nounwind readnone {
; CHECK-NEXT: fcmpu 1, 29, 0
; CHECK-NEXT: lwz 4, 156(1)
; CHECK-NEXT: crandc 20, 6, 0
; CHECK-NEXT: cror 20, 5, 20
; CHECK-NEXT: cror 24, 5, 20
; CHECK-NEXT: addis 3, 3, -32768
; CHECK-NEXT: bc 12, 20, .LBB0_4
; CHECK-NEXT: bc 12, 24, .LBB0_4
; CHECK-NEXT: # %bb.3: # %bb1
; CHECK-NEXT: ori 30, 4, 0
; CHECK-NEXT: b .LBB0_5
Expand Down Expand Up @@ -230,9 +230,9 @@ define i64 @__fixunstfdi(ppc_fp128 %a) nounwind readnone {
; CHECK-NEXT: fcmpu 1, 31, 0
; CHECK-NEXT: lwz 4, 28(1)
; CHECK-NEXT: crandc 20, 6, 1
; CHECK-NEXT: cror 20, 4, 20
; CHECK-NEXT: cror 24, 4, 20
; CHECK-NEXT: addis 3, 3, -32768
; CHECK-NEXT: bc 12, 20, .LBB0_13
; CHECK-NEXT: bc 12, 24, .LBB0_13
; CHECK-NEXT: # %bb.12: # %bb2
; CHECK-NEXT: ori 3, 4, 0
; CHECK-NEXT: b .LBB0_13
Expand Down Expand Up @@ -285,9 +285,9 @@ define i64 @__fixunstfdi(ppc_fp128 %a) nounwind readnone {
; CHECK-NEXT: fcmpu 1, 31, 0
; CHECK-NEXT: lwz 4, 92(1)
; CHECK-NEXT: crandc 20, 6, 0
; CHECK-NEXT: cror 20, 5, 20
; CHECK-NEXT: cror 24, 5, 20
; CHECK-NEXT: addis 3, 3, -32768
; CHECK-NEXT: bc 12, 20, .LBB0_15
; CHECK-NEXT: bc 12, 24, .LBB0_15
; CHECK-NEXT: b .LBB0_16
; CHECK-NEXT: .LBB0_15: # %bb3
; CHECK-NEXT: addi 4, 3, 0
Expand Down
22 changes: 11 additions & 11 deletions llvm/test/CodeGen/PowerPC/all-atomics.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -5687,16 +5687,16 @@ define dso_local i64 @atommax8(ptr nocapture noundef %ptr, i64 noundef %val) loc
; AIX32-NEXT: cmplw 5, 30
; AIX32-NEXT: cmpw 1, 5, 30
; AIX32-NEXT: li 7, 5
; AIX32-NEXT: li 8, 5
; AIX32-NEXT: cmplw 6, 4, 31
; AIX32-NEXT: stw 5, 56(1)
; AIX32-NEXT: mr 3, 29
; AIX32-NEXT: crandc 20, 5, 2
; AIX32-NEXT: cmplw 1, 4, 31
; AIX32-NEXT: crand 21, 2, 5
; AIX32-NEXT: crand 28, 2, 25
; AIX32-NEXT: li 8, 5
; AIX32-NEXT: stw 4, 60(1)
; AIX32-NEXT: cror 20, 21, 20
; AIX32-NEXT: isel 5, 5, 30, 20
; AIX32-NEXT: isel 6, 4, 31, 20
; AIX32-NEXT: cror 4, 28, 20
; AIX32-NEXT: isel 5, 5, 30, 4
; AIX32-NEXT: isel 6, 4, 31, 4
; AIX32-NEXT: mr 4, 28
; AIX32-NEXT: bl .__atomic_compare_exchange_8[PR]
; AIX32-NEXT: nop
Expand All @@ -5708,16 +5708,16 @@ define dso_local i64 @atommax8(ptr nocapture noundef %ptr, i64 noundef %val) loc
; AIX32-NEXT: cmplw 5, 30
; AIX32-NEXT: cmpw 1, 5, 30
; AIX32-NEXT: li 3, 55
; AIX32-NEXT: cmplw 6, 4, 31
; AIX32-NEXT: lwz 31, 76(1) # 4-byte Folded Reload
; AIX32-NEXT: lwz 30, 72(1) # 4-byte Folded Reload
; AIX32-NEXT: lwz 29, 68(1) # 4-byte Folded Reload
; AIX32-NEXT: lwz 28, 64(1) # 4-byte Folded Reload
; AIX32-NEXT: crandc 20, 5, 2
; AIX32-NEXT: cmplw 1, 4, 31
; AIX32-NEXT: crand 28, 2, 25
; AIX32-NEXT: li 4, 66
; AIX32-NEXT: lwz 31, 76(1) # 4-byte Folded Reload
; AIX32-NEXT: crand 21, 2, 5
; AIX32-NEXT: cror 20, 21, 20
; AIX32-NEXT: isel 4, 4, 3, 20
; AIX32-NEXT: cror 4, 28, 20
; AIX32-NEXT: isel 4, 4, 3, 4
; AIX32-NEXT: li 3, 0
; AIX32-NEXT: addi 1, 1, 80
; AIX32-NEXT: lwz 0, 8(1)
Expand Down
22 changes: 11 additions & 11 deletions llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-compare.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -9,24 +9,24 @@
; RUN: -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK-64

define dso_local signext i32 @test_builtin_ppc_cmprb(i32 %a, i32%b, i32 %c, i32%d) {
; CHECK-32-LABEL: test_builtin_ppc_cmprb:
; CHECK-32: # %bb.0: # %entry
; CHECK-32-NEXT: cmprb 0, 0, 3, 4
; CHECK-32-NEXT: setb 3, 0
; CHECK-32-NEXT: cmprb 0, 1, 5, 6
; CHECK-32-NEXT: setb 4, 0
; CHECK-32-NEXT: add 3, 3, 4
; CHECK-32-NEXT: blr
;
; CHECK-64-LABEL: test_builtin_ppc_cmprb:
; CHECK-64: # %bb.0: # %entry
; CHECK-64-NEXT: cmprb 0, 0, 3, 4
; CHECK-64-NEXT: cmprb 1, 1, 5, 6
; CHECK-64-NEXT: setb 3, 0
; CHECK-64-NEXT: cmprb 0, 1, 5, 6
; CHECK-64-NEXT: setb 4, 0
; CHECK-64-NEXT: setb 4, 1
; CHECK-64-NEXT: add 3, 3, 4
; CHECK-64-NEXT: extsw 3, 3
; CHECK-64-NEXT: blr
;
; CHECK-32-LABEL: test_builtin_ppc_cmprb:
; CHECK-32: # %bb.0: # %entry
; CHECK-32-NEXT: cmprb 0, 0, 3, 4
; CHECK-32-NEXT: cmprb 1, 1, 5, 6
; CHECK-32-NEXT: setb 3, 0
; CHECK-32-NEXT: setb 4, 1
; CHECK-32-NEXT: add 3, 3, 4
; CHECK-32-NEXT: blr
entry:
%0 = call i32 @llvm.ppc.cmprb(i32 0, i32 %a, i32 %b)
%1 = call i32 @llvm.ppc.cmprb(i32 1, i32 %c, i32 %d)
Expand Down
24 changes: 12 additions & 12 deletions llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-maxmin.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -10,8 +10,8 @@ define ppc_fp128 @test_maxfe(ppc_fp128 %a, ppc_fp128 %b, ppc_fp128 %c, ppc_fp128
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fcmpu 0, 6, 4
; CHECK-NEXT: fcmpu 1, 5, 3
; CHECK-NEXT: crand 20, 6, 1
; CHECK-NEXT: cror 20, 5, 20
; CHECK-NEXT: crand 24, 6, 1
; CHECK-NEXT: cror 20, 5, 24
; CHECK-NEXT: bc 12, 20, .LBB0_2
; CHECK-NEXT: # %bb.1: # %entry
; CHECK-NEXT: fmr 6, 4
Expand All @@ -22,8 +22,8 @@ define ppc_fp128 @test_maxfe(ppc_fp128 %a, ppc_fp128 %b, ppc_fp128 %c, ppc_fp128
; CHECK-NEXT: fmr 5, 3
; CHECK-NEXT: .LBB0_4: # %entry
; CHECK-NEXT: fcmpu 1, 5, 1
; CHECK-NEXT: crand 20, 6, 1
; CHECK-NEXT: cror 20, 5, 20
; CHECK-NEXT: crand 24, 6, 1
; CHECK-NEXT: cror 20, 5, 24
; CHECK-NEXT: bc 12, 20, .LBB0_6
; CHECK-NEXT: # %bb.5: # %entry
; CHECK-NEXT: fmr 6, 2
Expand All @@ -34,8 +34,8 @@ define ppc_fp128 @test_maxfe(ppc_fp128 %a, ppc_fp128 %b, ppc_fp128 %c, ppc_fp128
; CHECK-NEXT: fmr 5, 1
; CHECK-NEXT: .LBB0_8: # %entry
; CHECK-NEXT: fcmpu 1, 5, 7
; CHECK-NEXT: crand 20, 6, 1
; CHECK-NEXT: cror 20, 5, 20
; CHECK-NEXT: crand 24, 6, 1
; CHECK-NEXT: cror 20, 5, 24
; CHECK-NEXT: bc 12, 20, .LBB0_10
; CHECK-NEXT: # %bb.9: # %entry
; CHECK-NEXT: fmr 5, 7
Expand Down Expand Up @@ -136,8 +136,8 @@ define ppc_fp128 @test_minfe(ppc_fp128 %a, ppc_fp128 %b, ppc_fp128 %c, ppc_fp128
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fcmpu 0, 6, 4
; CHECK-NEXT: fcmpu 1, 5, 3
; CHECK-NEXT: crand 20, 6, 0
; CHECK-NEXT: cror 20, 4, 20
; CHECK-NEXT: crand 24, 6, 0
; CHECK-NEXT: cror 20, 4, 24
; CHECK-NEXT: bc 12, 20, .LBB3_2
; CHECK-NEXT: # %bb.1: # %entry
; CHECK-NEXT: fmr 6, 4
Expand All @@ -148,8 +148,8 @@ define ppc_fp128 @test_minfe(ppc_fp128 %a, ppc_fp128 %b, ppc_fp128 %c, ppc_fp128
; CHECK-NEXT: fmr 5, 3
; CHECK-NEXT: .LBB3_4: # %entry
; CHECK-NEXT: fcmpu 1, 5, 1
; CHECK-NEXT: crand 20, 6, 0
; CHECK-NEXT: cror 20, 4, 20
; CHECK-NEXT: crand 24, 6, 0
; CHECK-NEXT: cror 20, 4, 24
; CHECK-NEXT: bc 12, 20, .LBB3_6
; CHECK-NEXT: # %bb.5: # %entry
; CHECK-NEXT: fmr 6, 2
Expand All @@ -160,8 +160,8 @@ define ppc_fp128 @test_minfe(ppc_fp128 %a, ppc_fp128 %b, ppc_fp128 %c, ppc_fp128
; CHECK-NEXT: fmr 5, 1
; CHECK-NEXT: .LBB3_8: # %entry
; CHECK-NEXT: fcmpu 1, 5, 7
; CHECK-NEXT: crand 20, 6, 0
; CHECK-NEXT: cror 20, 4, 20
; CHECK-NEXT: crand 24, 6, 0
; CHECK-NEXT: cror 20, 4, 24
; CHECK-NEXT: bc 12, 20, .LBB3_10
; CHECK-NEXT: # %bb.9: # %entry
; CHECK-NEXT: fmr 5, 7
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/PowerPC/common-chain-aix32.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -38,10 +38,10 @@ define i64 @two_chain_same_offset_succ_i32(ptr %p, i32 %offset, i32 %base1, i64
; CHECK-LABEL: two_chain_same_offset_succ_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cmplwi r6, 0
; CHECK-NEXT: cmpwi cr1, r6, 0
; CHECK-NEXT: crandc 4*cr5+lt, 4*cr1+lt, eq
; CHECK-NEXT: cmpwi cr5, r6, 0
; CHECK-NEXT: cmpwi cr1, r7, 0
; CHECK-NEXT: bc 12, 4*cr5+lt, L..BB0_6
; CHECK-NEXT: crandc 4*cr6+lt, 4*cr5+lt, eq
; CHECK-NEXT: bc 12, 4*cr6+lt, L..BB0_6
; CHECK-NEXT: # %bb.1: # %entry
; CHECK-NEXT: crand 4*cr5+lt, eq, 4*cr1+eq
; CHECK-NEXT: bc 12, 4*cr5+lt, L..BB0_6
Expand Down
24 changes: 12 additions & 12 deletions llvm/test/CodeGen/PowerPC/crbit-asm.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -16,9 +16,9 @@ define zeroext i1 @testi1(i1 zeroext %b1, i1 zeroext %b2) #0 {
; CHECK-NEXT: li 3, 0
; CHECK-NEXT: li 4, 1
; CHECK-NEXT: #APP
; CHECK-NEXT: crand 20, 20, 1
; CHECK-NEXT: crand 24, 20, 1
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: isel 3, 4, 3, 20
; CHECK-NEXT: isel 3, 4, 3, 24
; CHECK-NEXT: blr
;
; CHECK-NO-ISEL-LABEL: testi1:
Expand All @@ -29,9 +29,9 @@ define zeroext i1 @testi1(i1 zeroext %b1, i1 zeroext %b2) #0 {
; CHECK-NO-ISEL-NEXT: li 3, 0
; CHECK-NO-ISEL-NEXT: li 4, 1
; CHECK-NO-ISEL-NEXT: #APP
; CHECK-NO-ISEL-NEXT: crand 20, 20, 1
; CHECK-NO-ISEL-NEXT: crand 24, 20, 1
; CHECK-NO-ISEL-NEXT: #NO_APP
; CHECK-NO-ISEL-NEXT: bc 12, 20, .LBB0_1
; CHECK-NO-ISEL-NEXT: bc 12, 24, .LBB0_1
; CHECK-NO-ISEL-NEXT: blr
; CHECK-NO-ISEL-NEXT: .LBB0_1: # %entry
; CHECK-NO-ISEL-NEXT: addi 3, 4, 0
Expand All @@ -53,9 +53,9 @@ define signext i32 @testi32(i32 signext %b1, i32 signext %b2) #0 {
; CHECK-NEXT: li 3, 0
; CHECK-NEXT: li 4, -1
; CHECK-NEXT: #APP
; CHECK-NEXT: crand 20, 20, 1
; CHECK-NEXT: crand 24, 20, 1
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: isel 3, 4, 3, 20
; CHECK-NEXT: isel 3, 4, 3, 24
; CHECK-NEXT: blr
;
; CHECK-NO-ISEL-LABEL: testi32:
Expand All @@ -66,9 +66,9 @@ define signext i32 @testi32(i32 signext %b1, i32 signext %b2) #0 {
; CHECK-NO-ISEL-NEXT: li 3, 0
; CHECK-NO-ISEL-NEXT: li 4, -1
; CHECK-NO-ISEL-NEXT: #APP
; CHECK-NO-ISEL-NEXT: crand 20, 20, 1
; CHECK-NO-ISEL-NEXT: crand 24, 20, 1
; CHECK-NO-ISEL-NEXT: #NO_APP
; CHECK-NO-ISEL-NEXT: bc 12, 20, .LBB1_1
; CHECK-NO-ISEL-NEXT: bc 12, 24, .LBB1_1
; CHECK-NO-ISEL-NEXT: blr
; CHECK-NO-ISEL-NEXT: .LBB1_1: # %entry
; CHECK-NO-ISEL-NEXT: addi 3, 4, 0
Expand All @@ -91,9 +91,9 @@ define zeroext i8 @testi8(i8 zeroext %b1, i8 zeroext %b2) #0 {
; CHECK-NEXT: li 3, 0
; CHECK-NEXT: li 4, 1
; CHECK-NEXT: #APP
; CHECK-NEXT: crand 20, 20, 1
; CHECK-NEXT: crand 24, 20, 1
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: isel 3, 4, 3, 20
; CHECK-NEXT: isel 3, 4, 3, 24
; CHECK-NEXT: blr
;
; CHECK-NO-ISEL-LABEL: testi8:
Expand All @@ -104,9 +104,9 @@ define zeroext i8 @testi8(i8 zeroext %b1, i8 zeroext %b2) #0 {
; CHECK-NO-ISEL-NEXT: li 3, 0
; CHECK-NO-ISEL-NEXT: li 4, 1
; CHECK-NO-ISEL-NEXT: #APP
; CHECK-NO-ISEL-NEXT: crand 20, 20, 1
; CHECK-NO-ISEL-NEXT: crand 24, 20, 1
; CHECK-NO-ISEL-NEXT: #NO_APP
; CHECK-NO-ISEL-NEXT: bc 12, 20, .LBB2_1
; CHECK-NO-ISEL-NEXT: bc 12, 24, .LBB2_1
; CHECK-NO-ISEL-NEXT: blr
; CHECK-NO-ISEL-NEXT: .LBB2_1: # %entry
; CHECK-NO-ISEL-NEXT: addi 3, 4, 0
Expand Down
Loading