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[RISCV][llvm-mca] Vector Unit Stride Loads and stores use EEW and EMU… #69409

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Merged
merged 5 commits into from
Oct 20, 2023
Merged

[RISCV][llvm-mca] Vector Unit Stride Loads and stores use EEW and EMU… #69409

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1a5d4a8
[RISCV][llvm-mca] Vector Unit Stride Loads and stores use EEW and EMU…
michaelmaitland Oct 18, 2023
a3ef167
Use static cast for LMUL to/from VLMUL
michaelmaitland Oct 18, 2023
76decd1
Don't use GCD to calculate EMUL
michaelmaitland Oct 18, 2023
90bfd7a
Use getSameRatioLMUL
michaelmaitland Oct 19, 2023
5956b08
remove blank line
michaelmaitland Oct 20, 2023
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55 changes: 49 additions & 6 deletions llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -185,6 +185,38 @@ RISCVInstrumentManager::createInstruments(const MCInst &Inst) {
return SmallVector<UniqueInstrument>();
}

static std::pair<uint8_t, uint8_t>
getEEWAndEMULForUnitStrideLoadStore(unsigned Opcode, RISCVII::VLMUL LMUL,
uint8_t SEW) {
uint8_t EEW;
switch (Opcode) {
case RISCV::VLM_V:
case RISCV::VSM_V:
case RISCV::VLE8_V:
case RISCV::VSE8_V:
EEW = 8;
break;
case RISCV::VLE16_V:
case RISCV::VSE16_V:
EEW = 16;
break;
case RISCV::VLE32_V:
case RISCV::VSE32_V:
EEW = 32;
break;
case RISCV::VLE64_V:
case RISCV::VSE64_V:
EEW = 64;
break;
default:
llvm_unreachable("Opcode is not a vector unit stride load nor store");
}

uint8_t EMUL =
static_cast<uint8_t>(RISCVVType::getSameRatioLMUL(SEW, LMUL, EEW));
return std::make_pair(EEW, EMUL);
}

unsigned RISCVInstrumentManager::getSchedClassID(
const MCInstrInfo &MCII, const MCInst &MCI,
const llvm::SmallVector<Instrument *> &IVec) const {
Expand Down Expand Up @@ -214,12 +246,23 @@ unsigned RISCVInstrumentManager::getSchedClassID(
// or (Opcode, LMUL, SEW) if SEW instrument is active, and depends on LMUL
// and SEW, or (Opcode, LMUL, 0) if does not depend on SEW.
uint8_t SEW = SI ? SI->getSEW() : 0;
// Check if it depends on LMUL and SEW
const RISCVVInversePseudosTable::PseudoInfo *RVV =
RISCVVInversePseudosTable::getBaseInfo(Opcode, LMUL, SEW);
// Check if it depends only on LMUL
if (!RVV)
RVV = RISCVVInversePseudosTable::getBaseInfo(Opcode, LMUL, 0);

const RISCVVInversePseudosTable::PseudoInfo *RVV = nullptr;
if (Opcode == RISCV::VLM_V || Opcode == RISCV::VSM_V ||
Opcode == RISCV::VLE8_V || Opcode == RISCV::VSE8_V ||
Opcode == RISCV::VLE16_V || Opcode == RISCV::VSE16_V ||
Opcode == RISCV::VLE32_V || Opcode == RISCV::VSE32_V ||
Opcode == RISCV::VLE64_V || Opcode == RISCV::VSE64_V) {
RISCVII::VLMUL VLMUL = static_cast<RISCVII::VLMUL>(LMUL);
auto [EEW, EMUL] = getEEWAndEMULForUnitStrideLoadStore(Opcode, VLMUL, SEW);
RVV = RISCVVInversePseudosTable::getBaseInfo(Opcode, EMUL, EEW);
} else {
// Check if it depends on LMUL and SEW
RVV = RISCVVInversePseudosTable::getBaseInfo(Opcode, LMUL, SEW);
// Check if it depends only on LMUL
if (!RVV)
RVV = RISCVVInversePseudosTable::getBaseInfo(Opcode, LMUL, 0);
}

// Not a RVV instr
if (!RVV) {
Expand Down
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