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[AMDGPU] Make S_MOV_B64_IMM_PSEUDO foldable #69483

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Merged
merged 2 commits into from
Oct 18, 2023
Merged

[AMDGPU] Make S_MOV_B64_IMM_PSEUDO foldable #69483

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27ab573
[AMDGPU] Make S_MOV_B64_IMM_PSEUDO foldable
rampitec Oct 18, 2023
2360647
Merge branch 'llvm:main' into fold-s-mov-b64-imm-pseudo
rampitec Oct 18, 2023
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1 change: 1 addition & 0 deletions llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -3170,6 +3170,7 @@ bool SIInstrInfo::isFoldableCopy(const MachineInstr &MI) {
case AMDGPU::V_MOV_B64_e64:
case AMDGPU::S_MOV_B32:
case AMDGPU::S_MOV_B64:
case AMDGPU::S_MOV_B64_IMM_PSEUDO:
case AMDGPU::COPY:
case AMDGPU::WWM_COPY:
case AMDGPU::V_ACCVGPR_WRITE_B32_e64:
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14 changes: 7 additions & 7 deletions llvm/test/CodeGen/AMDGPU/fold-short-64-bit-literals.mir
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Expand Up @@ -9,11 +9,11 @@ body: |

; GCN-LABEL: name: no_fold_fp_64bit_literal_sgpr
; GCN: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
; GCN-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 1311768467750121200
; GCN-NEXT: [[V_ADD_F64_e64_:%[0-9]+]]:vreg_64 = V_ADD_F64_e64 0, [[S_MOV_B64_]], 0, [[DEF]], 0, 0, implicit $mode, implicit $exec
; GCN-NEXT: [[S_MOV_B:%[0-9]+]]:sreg_64 = S_MOV_B64_IMM_PSEUDO 1311768467750121200
; GCN-NEXT: [[V_ADD_F64_e64_:%[0-9]+]]:vreg_64 = V_ADD_F64_e64 0, [[S_MOV_B]], 0, [[DEF]], 0, 0, implicit $mode, implicit $exec
; GCN-NEXT: SI_RETURN_TO_EPILOG [[V_ADD_F64_e64_]]
%0:vreg_64 = IMPLICIT_DEF
%1:sreg_64 = S_MOV_B64 1311768467750121200
%1:sreg_64 = S_MOV_B64_IMM_PSEUDO 1311768467750121200
%2:vreg_64 = V_ADD_F64_e64 0, %1, 0, %0, 0, 0, implicit $mode, implicit $exec
SI_RETURN_TO_EPILOG %2
...
Expand Down Expand Up @@ -46,7 +46,7 @@ body: |
; GCN-NEXT: [[V_ADD_F64_e64_:%[0-9]+]]:vreg_64 = V_ADD_F64_e64 0, 4636737291354636288, 0, [[DEF]], 0, 0, implicit $mode, implicit $exec
; GCN-NEXT: SI_RETURN_TO_EPILOG [[V_ADD_F64_e64_]]
%0:vreg_64 = IMPLICIT_DEF
%1:sreg_64 = S_MOV_B64 4636737291354636288
%1:sreg_64 = S_MOV_B64_IMM_PSEUDO 4636737291354636288
%2:vreg_64 = V_ADD_F64_e64 0, %1, 0, %0, 0, 0, implicit $mode, implicit $exec
SI_RETURN_TO_EPILOG %2
...
Expand All @@ -59,11 +59,11 @@ body: |

; GCN-LABEL: name: no_fold_int_64bit_literal_sgpr
; GCN: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
; GCN-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 1311768467750121200
; GCN-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[DEF]], [[S_MOV_B64_]], implicit-def $scc
; GCN-NEXT: [[S_MOV_B:%[0-9]+]]:sreg_64 = S_MOV_B64_IMM_PSEUDO 1311768467750121200
; GCN-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[DEF]], [[S_MOV_B]], implicit-def $scc
; GCN-NEXT: SI_RETURN_TO_EPILOG [[S_AND_B64_]]
%0:sreg_64 = IMPLICIT_DEF
%1:sreg_64 = S_MOV_B64 1311768467750121200
%1:sreg_64 = S_MOV_B64_IMM_PSEUDO 1311768467750121200
%2:sreg_64 = S_AND_B64 %0, %1, implicit-def $scc
SI_RETURN_TO_EPILOG %2
...
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