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[RISCV] Combine (and (select cond, x, -1), c) to (select cond, x, (and x, c)) with Zicond. #69563

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Merged
merged 2 commits into from
Oct 19, 2023
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[RISCV] Combine (and (select cond, x, -1), c) to (select cond, x, (and x, c)) with Zicond. #69563

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[RISCV] Combine (and (select cond, x, -1), c) to (select cond, x, (an…
Oct 19, 2023
ee9e15c
[RISCV] Refine test case and fix typo.
Oct 19, 2023
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19 changes: 17 additions & 2 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -11584,8 +11584,23 @@ static SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
if (VT.isVector())
return SDValue();

if (!Subtarget.hasShortForwardBranchOpt() ||
(Slct.getOpcode() != ISD::SELECT &&
if (!Subtarget.hasShortForwardBranchOpt()) {
// (select cond, x, (and x, c)) has custom lowering with Zicond.
if ((!Subtarget.hasStdExtZicond() &&
!Subtarget.hasVendorXVentanaCondOps()) ||
N->getOpcode() != ISD::AND)
return SDValue();

// Maybe harmful when condition code has multiple use.
if (Slct.getOpcode() == ISD::SELECT && !Slct.getOperand(0).hasOneUse())
return SDValue();

// Maybe harmful when VT is wider than XLen.
if (VT.getSizeInBits() > Subtarget.getXLen())
return SDValue();
}

if ((Slct.getOpcode() != ISD::SELECT &&
Slct.getOpcode() != RISCVISD::SELECT_CC) ||
!Slct.hasOneUse())
return SDValue();
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