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[GISel] Pass MPO and VA to assignValueToAddress by const reference. NFC #69810

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Merged
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Oct 24, 2023
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[GISel] Pass MPO and VA to assignValueToAddress by const reference. NFC #69810

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10 changes: 5 additions & 5 deletions llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h
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Expand Up @@ -274,16 +274,16 @@ class CallLowering {
/// location. Load or store it there, with appropriate extension
/// if necessary.
virtual void assignValueToAddress(Register ValVReg, Register Addr,
LLT MemTy, MachinePointerInfo &MPO,
CCValAssign &VA) = 0;
LLT MemTy, const MachinePointerInfo &MPO,
const CCValAssign &VA) = 0;

/// An overload which takes an ArgInfo if additional information about the
/// arg is needed. \p ValRegIndex is the index in \p Arg.Regs for the value
/// to store.
virtual void assignValueToAddress(const ArgInfo &Arg, unsigned ValRegIndex,
Register Addr, LLT MemTy,
MachinePointerInfo &MPO,
CCValAssign &VA) {
const MachinePointerInfo &MPO,
const CCValAssign &VA) {
assignValueToAddress(Arg.Regs[ValRegIndex], Addr, MemTy, MPO, VA);
}

Expand Down Expand Up @@ -311,7 +311,7 @@ class CallLowering {

/// Extend a register to the location type given in VA, capped at extending
/// to at most MaxSize bits. If MaxSizeBits is 0 then no maximum is set.
Register extendRegister(Register ValReg, CCValAssign &VA,
Register extendRegister(Register ValReg, const CCValAssign &VA,
unsigned MaxSizeBits = 0);
};

Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
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Expand Up @@ -1135,7 +1135,7 @@ void CallLowering::ValueHandler::copyArgumentMemory(
}

Register CallLowering::ValueHandler::extendRegister(Register ValReg,
CCValAssign &VA,
const CCValAssign &VA,
unsigned MaxSizeBits) {
LLT LocTy{VA.getLocVT()};
LLT ValTy{VA.getValVT()};
Expand Down
11 changes: 7 additions & 4 deletions llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
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Expand Up @@ -164,7 +164,8 @@ struct IncomingArgHandler : public CallLowering::IncomingValueHandler {
}

void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
MachinePointerInfo &MPO, CCValAssign &VA) override {
const MachinePointerInfo &MPO,
const CCValAssign &VA) override {
MachineFunction &MF = MIRBuilder.getMF();

LLT ValTy(VA.getValVT());
Expand Down Expand Up @@ -290,16 +291,18 @@ struct OutgoingArgHandler : public CallLowering::OutgoingValueHandler {
}

void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
MachinePointerInfo &MPO, CCValAssign &VA) override {
const MachinePointerInfo &MPO,
const CCValAssign &VA) override {
MachineFunction &MF = MIRBuilder.getMF();
auto MMO = MF.getMachineMemOperand(MPO, MachineMemOperand::MOStore, MemTy,
inferAlignFromPtrInfo(MF, MPO));
MIRBuilder.buildStore(ValVReg, Addr, *MMO);
}

void assignValueToAddress(const CallLowering::ArgInfo &Arg, unsigned RegIndex,
Register Addr, LLT MemTy, MachinePointerInfo &MPO,
CCValAssign &VA) override {
Register Addr, LLT MemTy,
const MachinePointerInfo &MPO,
const CCValAssign &VA) override {
unsigned MaxSize = MemTy.getSizeInBytes() * 8;
// For varargs, we always want to extend them to 8 bytes, in which case
// we disable setting a max.
Expand Down
14 changes: 9 additions & 5 deletions llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
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Expand Up @@ -32,7 +32,7 @@ namespace {

/// Wrapper around extendRegister to ensure we extend to a full 32-bit register.
static Register extendRegisterMin32(CallLowering::ValueHandler &Handler,
Register ValVReg, CCValAssign &VA) {
Register ValVReg, const CCValAssign &VA) {
if (VA.getLocVT().getSizeInBits() < 32) {
// 16-bit types are reported as legal for 32-bit registers. We need to
// extend and do a 32-bit copy to avoid the verifier complaining about it.
Expand All @@ -56,7 +56,8 @@ struct AMDGPUOutgoingValueHandler : public CallLowering::OutgoingValueHandler {
}

void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
MachinePointerInfo &MPO, CCValAssign &VA) override {
const MachinePointerInfo &MPO,
const CCValAssign &VA) override {
llvm_unreachable("not implemented");
}

Expand Down Expand Up @@ -137,7 +138,8 @@ struct AMDGPUIncomingArgHandler : public CallLowering::IncomingValueHandler {
}

void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
MachinePointerInfo &MPO, CCValAssign &VA) override {
const MachinePointerInfo &MPO,
const CCValAssign &VA) override {
MachineFunction &MF = MIRBuilder.getMF();

auto MMO = MF.getMachineMemOperand(
Expand Down Expand Up @@ -236,7 +238,8 @@ struct AMDGPUOutgoingArgHandler : public AMDGPUOutgoingValueHandler {
}

void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
MachinePointerInfo &MPO, CCValAssign &VA) override {
const MachinePointerInfo &MPO,
const CCValAssign &VA) override {
MachineFunction &MF = MIRBuilder.getMF();
uint64_t LocMemOffset = VA.getLocMemOffset();
const auto &ST = MF.getSubtarget<GCNSubtarget>();
Expand All @@ -249,7 +252,8 @@ struct AMDGPUOutgoingArgHandler : public AMDGPUOutgoingValueHandler {

void assignValueToAddress(const CallLowering::ArgInfo &Arg,
unsigned ValRegIndex, Register Addr, LLT MemTy,
MachinePointerInfo &MPO, CCValAssign &VA) override {
const MachinePointerInfo &MPO,
const CCValAssign &VA) override {
Register ValVReg = VA.getLocInfo() != CCValAssign::LocInfo::FPExt
? extendRegister(Arg.Regs[ValRegIndex], VA)
: Arg.Regs[ValRegIndex];
Expand Down
8 changes: 5 additions & 3 deletions llvm/lib/Target/ARM/ARMCallLowering.cpp
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Expand Up @@ -123,7 +123,8 @@ struct ARMOutgoingValueHandler : public CallLowering::OutgoingValueHandler {
}

void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
MachinePointerInfo &MPO, CCValAssign &VA) override {
const MachinePointerInfo &MPO,
const CCValAssign &VA) override {
Register ExtReg = extendRegister(ValVReg, VA);
auto MMO = MIRBuilder.getMF().getMachineMemOperand(
MPO, MachineMemOperand::MOStore, MemTy, Align(1));
Expand Down Expand Up @@ -255,7 +256,8 @@ struct ARMIncomingValueHandler : public CallLowering::IncomingValueHandler {
}

void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
MachinePointerInfo &MPO, CCValAssign &VA) override {
const MachinePointerInfo &MPO,
const CCValAssign &VA) override {
if (VA.getLocInfo() == CCValAssign::SExt ||
VA.getLocInfo() == CCValAssign::ZExt) {
// If the value is zero- or sign-extended, its size becomes 4 bytes, so
Expand All @@ -272,7 +274,7 @@ struct ARMIncomingValueHandler : public CallLowering::IncomingValueHandler {
}

MachineInstrBuilder buildLoad(const DstOp &Res, Register Addr, LLT MemTy,
MachinePointerInfo &MPO) {
const MachinePointerInfo &MPO) {
MachineFunction &MF = MIRBuilder.getMF();

auto MMO = MF.getMachineMemOperand(MPO, MachineMemOperand::MOLoad, MemTy,
Expand Down
11 changes: 5 additions & 6 deletions llvm/lib/Target/M68k/GISel/M68kCallLowering.cpp
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Expand Up @@ -43,7 +43,8 @@ struct M68kOutgoingArgHandler : public CallLowering::OutgoingValueHandler {
}

void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
MachinePointerInfo &MPO, CCValAssign &VA) override {
const MachinePointerInfo &MPO,
const CCValAssign &VA) override {
MachineFunction &MF = MIRBuilder.getMF();
Register ExtReg = extendRegister(ValVReg, VA);

Expand Down Expand Up @@ -132,11 +133,9 @@ void M68kIncomingValueHandler::assignValueToReg(Register ValVReg,
IncomingValueHandler::assignValueToReg(ValVReg, PhysReg, VA);
}

void M68kIncomingValueHandler::assignValueToAddress(Register ValVReg,
Register Addr,
LLT MemTy,
MachinePointerInfo &MPO,
CCValAssign &VA) {
void M68kIncomingValueHandler::assignValueToAddress(
Register ValVReg, Register Addr, LLT MemTy, const MachinePointerInfo &MPO,
const CCValAssign &VA) {
MachineFunction &MF = MIRBuilder.getMF();
auto *MMO = MF.getMachineMemOperand(MPO, MachineMemOperand::MOLoad, MemTy,
inferAlignFromPtrInfo(MF, MPO));
Expand Down
3 changes: 2 additions & 1 deletion llvm/lib/Target/M68k/GISel/M68kCallLowering.h
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Expand Up @@ -56,7 +56,8 @@ struct M68kIncomingValueHandler : public CallLowering::IncomingValueHandler {
CCValAssign VA) override;

void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
MachinePointerInfo &MPO, CCValAssign &VA) override;
const MachinePointerInfo &MPO,
const CCValAssign &VA) override;

Register getStackAddress(uint64_t Size, int64_t Offset,
MachinePointerInfo &MPO,
Expand Down
20 changes: 10 additions & 10 deletions llvm/lib/Target/Mips/MipsCallLowering.cpp
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Expand Up @@ -99,7 +99,8 @@ class MipsIncomingValueHandler : public CallLowering::IncomingValueHandler {
MachinePointerInfo &MPO,
ISD::ArgFlagsTy Flags) override;
void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
MachinePointerInfo &MPO, CCValAssign &VA) override;
const MachinePointerInfo &MPO,
const CCValAssign &VA) override;

unsigned assignCustomValue(CallLowering::ArgInfo &Arg,
ArrayRef<CCValAssign> VAs,
Expand Down Expand Up @@ -149,10 +150,9 @@ Register MipsIncomingValueHandler::getStackAddress(uint64_t Size,
return MIRBuilder.buildFrameIndex(LLT::pointer(0, 32), FI).getReg(0);
}

void MipsIncomingValueHandler::assignValueToAddress(Register ValVReg,
Register Addr, LLT MemTy,
MachinePointerInfo &MPO,
CCValAssign &VA) {
void MipsIncomingValueHandler::assignValueToAddress(
Register ValVReg, Register Addr, LLT MemTy, const MachinePointerInfo &MPO,
const CCValAssign &VA) {
MachineFunction &MF = MIRBuilder.getMF();
auto MMO = MF.getMachineMemOperand(MPO, MachineMemOperand::MOLoad, MemTy,
inferAlignFromPtrInfo(MF, MPO));
Expand Down Expand Up @@ -207,7 +207,8 @@ class MipsOutgoingValueHandler : public CallLowering::OutgoingValueHandler {
ISD::ArgFlagsTy Flags) override;

void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
MachinePointerInfo &MPO, CCValAssign &VA) override;
const MachinePointerInfo &MPO,
const CCValAssign &VA) override;
unsigned assignCustomValue(CallLowering::ArgInfo &Arg,
ArrayRef<CCValAssign> VAs,
std::function<void()> *Thunk) override;
Expand Down Expand Up @@ -240,10 +241,9 @@ Register MipsOutgoingValueHandler::getStackAddress(uint64_t Size,
return AddrReg.getReg(0);
}

void MipsOutgoingValueHandler::assignValueToAddress(Register ValVReg,
Register Addr, LLT MemTy,
MachinePointerInfo &MPO,
CCValAssign &VA) {
void MipsOutgoingValueHandler::assignValueToAddress(
Register ValVReg, Register Addr, LLT MemTy, const MachinePointerInfo &MPO,
const CCValAssign &VA) {
MachineFunction &MF = MIRBuilder.getMF();
uint64_t LocMemOffset = VA.getLocMemOffset();

Expand Down
19 changes: 10 additions & 9 deletions llvm/lib/Target/PowerPC/GISel/PPCCallLowering.cpp
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Expand Up @@ -38,7 +38,8 @@ struct OutgoingArgHandler : public CallLowering::OutgoingValueHandler {
void assignValueToReg(Register ValVReg, Register PhysReg,
CCValAssign VA) override;
void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
MachinePointerInfo &MPO, CCValAssign &VA) override;
const MachinePointerInfo &MPO,
const CCValAssign &VA) override;
Register getStackAddress(uint64_t Size, int64_t Offset,
MachinePointerInfo &MPO,
ISD::ArgFlagsTy Flags) override;
Expand All @@ -56,8 +57,8 @@ void OutgoingArgHandler::assignValueToReg(Register ValVReg, Register PhysReg,

void OutgoingArgHandler::assignValueToAddress(Register ValVReg, Register Addr,
LLT MemTy,
MachinePointerInfo &MPO,
CCValAssign &VA) {
const MachinePointerInfo &MPO,
const CCValAssign &VA) {
llvm_unreachable("unimplemented");
}

Expand Down Expand Up @@ -148,13 +149,13 @@ void PPCIncomingValueHandler::assignValueToReg(Register ValVReg,
IncomingValueHandler::assignValueToReg(ValVReg, PhysReg, VA);
}

void PPCIncomingValueHandler::assignValueToAddress(Register ValVReg,
Register Addr, LLT MemTy,
MachinePointerInfo &MPO,
CCValAssign &VA) {
void PPCIncomingValueHandler::assignValueToAddress(
Register ValVReg, Register Addr, LLT MemTy, const MachinePointerInfo &MPO,
const CCValAssign &VA) {
// define a lambda expression to load value
auto BuildLoad = [](MachineIRBuilder &MIRBuilder, MachinePointerInfo &MPO,
LLT MemTy, const DstOp &Res, Register Addr) {
auto BuildLoad = [](MachineIRBuilder &MIRBuilder,
const MachinePointerInfo &MPO, LLT MemTy,
const DstOp &Res, Register Addr) {
MachineFunction &MF = MIRBuilder.getMF();
auto *MMO = MF.getMachineMemOperand(MPO, MachineMemOperand::MOLoad, MemTy,
inferAlignFromPtrInfo(MF, MPO));
Expand Down
3 changes: 2 additions & 1 deletion llvm/lib/Target/PowerPC/GISel/PPCCallLowering.h
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Expand Up @@ -49,7 +49,8 @@ class PPCIncomingValueHandler : public CallLowering::IncomingValueHandler {
CCValAssign VA) override;

void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
MachinePointerInfo &MPO, CCValAssign &VA) override;
const MachinePointerInfo &MPO,
const CCValAssign &VA) override;

Register getStackAddress(uint64_t Size, int64_t Offset,
MachinePointerInfo &MPO,
Expand Down
6 changes: 4 additions & 2 deletions llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp
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Expand Up @@ -78,7 +78,8 @@ struct RISCVOutgoingValueHandler : public CallLowering::OutgoingValueHandler {
}

void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
MachinePointerInfo &MPO, CCValAssign &VA) override {
const MachinePointerInfo &MPO,
const CCValAssign &VA) override {
MachineFunction &MF = MIRBuilder.getMF();
uint64_t LocMemOffset = VA.getLocMemOffset();

Expand Down Expand Up @@ -155,7 +156,8 @@ struct RISCVIncomingValueHandler : public CallLowering::IncomingValueHandler {
}

void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
MachinePointerInfo &MPO, CCValAssign &VA) override {
const MachinePointerInfo &MPO,
const CCValAssign &VA) override {
MachineFunction &MF = MIRBuilder.getMF();
auto MMO = MF.getMachineMemOperand(MPO, MachineMemOperand::MOLoad, MemTy,
inferAlignFromPtrInfo(MF, MPO));
Expand Down
6 changes: 4 additions & 2 deletions llvm/lib/Target/X86/GISel/X86CallLowering.cpp
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Expand Up @@ -113,7 +113,8 @@ struct X86OutgoingValueHandler : public CallLowering::OutgoingValueHandler {
}

void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
MachinePointerInfo &MPO, CCValAssign &VA) override {
const MachinePointerInfo &MPO,
const CCValAssign &VA) override {
MachineFunction &MF = MIRBuilder.getMF();
Register ExtReg = extendRegister(ValVReg, VA);

Expand Down Expand Up @@ -201,7 +202,8 @@ struct X86IncomingValueHandler : public CallLowering::IncomingValueHandler {
}

void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
MachinePointerInfo &MPO, CCValAssign &VA) override {
const MachinePointerInfo &MPO,
const CCValAssign &VA) override {
MachineFunction &MF = MIRBuilder.getMF();
auto *MMO = MF.getMachineMemOperand(
MPO, MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant, MemTy,
Expand Down