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[mlir] Fix nvvm integration tests build error #70113

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Merged
merged 2 commits into from
Oct 24, 2023
Merged

[mlir] Fix nvvm integration tests build error #70113

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7e0020b
[mlir] Fix nvvm integration tests build error
grypp Oct 24, 2023
8f5fbff
remove kernel-index-bitwidth
grypp Oct 24, 2023
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2 changes: 1 addition & 1 deletion mlir/test/Integration/GPU/CUDA/TensorCore/sm80/transform-mma-sync-matmul-f16-f16-accum.mlir
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Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@
// RUN: mlir-opt %s \
// RUN: -transform-interpreter \
// RUN: -test-transform-dialect-erase-schedule \
// RUN: -test-lower-to-nvvm="kernel-index-bitwidth=32 cubin-chip=sm_80 cubin-features=+ptx76 cubin-format=%gpu_compilation_format" \
// RUN: -test-lower-to-nvvm="cubin-chip=sm_80 cubin-features=+ptx76 cubin-format=%gpu_compilation_format" \
// RUN: | mlir-cpu-runner \
// RUN: --shared-libs=%mlir_cuda_runtime \
// RUN: --shared-libs=%mlir_runner_utils \
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2 changes: 1 addition & 1 deletion mlir/test/Integration/GPU/CUDA/TensorCore/sm80/transform-mma-sync-matmul-f32.mlir
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Original file line number Diff line number Diff line change
Expand Up @@ -11,7 +11,7 @@
// RUN: mlir-opt %s \
// RUN: -transform-interpreter \
// RUN: -test-transform-dialect-erase-schedule \
// RUN: -test-lower-to-nvvm="kernel-index-bitwidth=32 cubin-chip=sm_80 cubin-features=+ptx76 cubin-format=%gpu_compilation_format" \
// RUN: -test-lower-to-nvvm="cubin-chip=sm_80 cubin-features=+ptx76 cubin-format=%gpu_compilation_format" \
// RUN: | mlir-cpu-runner \
// RUN: --shared-libs=%mlir_cuda_runtime \
// RUN: --shared-libs=%mlir_runner_utils \
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22 changes: 20 additions & 2 deletions mlir/test/lib/Dialect/GPU/TestLowerToNVVM.cpp
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Expand Up @@ -65,6 +65,18 @@ struct TestLowerToNVVMOptions
*this, "opt-level",
llvm::cl::desc("Optimization level for NVVM compilation"),
llvm::cl::init(2)};
PassOptions::Option<bool> kernelUseBarePtrCallConv{
*this, "kernel-bare-ptr-calling-convention",
llvm::cl::desc(
"Whether to use the bareptr calling convention on the kernel "
"(warning this should be false until the GPU layering is fixed)"),
llvm::cl::init(false)};
PassOptions::Option<bool> hostUseBarePtrCallConv{
*this, "host-bare-ptr-calling-convention",
llvm::cl::desc(
"Whether to use the bareptr calling convention on the host (warning "
"this should be false until the GPU layering is fixed)"),
llvm::cl::init(false)};
};

//===----------------------------------------------------------------------===//
Expand Down Expand Up @@ -105,7 +117,10 @@ void buildCommonPassPipeline(OpPassManager &pm,
void buildGpuPassPipeline(OpPassManager &pm,
const TestLowerToNVVMOptions &options) {
pm.addNestedPass<gpu::GPUModuleOp>(createStripDebugInfoPass());
pm.addNestedPass<gpu::GPUModuleOp>(createConvertGpuOpsToNVVMOps());
ConvertGpuOpsToNVVMOpsOptions opt;
opt.useBarePtrCallConv = options.kernelUseBarePtrCallConv;
opt.indexBitwidth = options.indexBitWidth;
pm.addNestedPass<gpu::GPUModuleOp>(createConvertGpuOpsToNVVMOps(opt));
pm.addNestedPass<gpu::GPUModuleOp>(createCanonicalizerPass());
pm.addNestedPass<gpu::GPUModuleOp>(createCSEPass());
pm.addNestedPass<gpu::GPUModuleOp>(createReconcileUnrealizedCastsPass());
Expand All @@ -116,7 +131,10 @@ void buildGpuPassPipeline(OpPassManager &pm,
//===----------------------------------------------------------------------===//
void buildHostPostPipeline(OpPassManager &pm,
const TestLowerToNVVMOptions &options) {
pm.addPass(createGpuToLLVMConversionPass());
GpuToLLVMConversionPassOptions opt;
opt.hostBarePtrCallConv = options.hostUseBarePtrCallConv;
opt.kernelBarePtrCallConv = options.kernelUseBarePtrCallConv;
pm.addPass(createGpuToLLVMConversionPass(opt));

GpuModuleToBinaryPassOptions gpuModuleToBinaryPassOptions;
gpuModuleToBinaryPassOptions.compilationTarget = options.cubinFormat;
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