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[RISCV] Use RISCVInstrInfo::movImm to implement most of RISCVPostRAExpandPseudo::expandMovImm #70389

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[RISCV] Use RISCVInstrInfo::movImm to implement most of RISCVPostRAExpandPseudo::expandMovImm #70389

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3f5e742
[RISCV] Refactor RISCVPostRAExpandPseudo::expandMovImm and RISCVInstr…
topperc Oct 26, 2023
6730ce1
[RISCV] Use RISCVInstrInfo::movImm to implement most of RISCVPostRAEx…
topperc Oct 26, 2023
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32 changes: 23 additions & 9 deletions llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -737,7 +737,8 @@ MachineInstr *RISCVInstrInfo::foldMemoryOperandImpl(
void RISCVInstrInfo::movImm(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
const DebugLoc &DL, Register DstReg, uint64_t Val,
MachineInstr::MIFlag Flag) const {
MachineInstr::MIFlag Flag, bool DstRenamable,
bool DstIsDead) const {
Register SrcReg = RISCV::X0;

if (!STI.is64Bit() && !isInt<32>(Val))
Expand All @@ -747,35 +748,48 @@ void RISCVInstrInfo::movImm(MachineBasicBlock &MBB,
RISCVMatInt::generateInstSeq(Val, STI.getFeatureBits());
assert(!Seq.empty());

bool SrcRenamable = false;
unsigned Num = 0;

for (const RISCVMatInt::Inst &Inst : Seq) {
bool LastItem = ++Num == Seq.size();
unsigned DstRegState = getDeadRegState(DstIsDead && LastItem) |
getRenamableRegState(DstRenamable);
unsigned SrcRegState = getKillRegState(SrcReg != RISCV::X0) |
getRenamableRegState(SrcRenamable);
switch (Inst.getOpndKind()) {
case RISCVMatInt::Imm:
BuildMI(MBB, MBBI, DL, get(Inst.getOpcode()), DstReg)
BuildMI(MBB, MBBI, DL, get(Inst.getOpcode()))
.addReg(DstReg, RegState::Define | DstRegState)
.addImm(Inst.getImm())
.setMIFlag(Flag);
break;
case RISCVMatInt::RegX0:
BuildMI(MBB, MBBI, DL, get(Inst.getOpcode()), DstReg)
.addReg(SrcReg, getKillRegState(SrcReg != RISCV::X0))
BuildMI(MBB, MBBI, DL, get(Inst.getOpcode()))
.addReg(DstReg, RegState::Define | DstRegState)
.addReg(SrcReg, SrcRegState)
.addReg(RISCV::X0)
.setMIFlag(Flag);
break;
case RISCVMatInt::RegReg:
BuildMI(MBB, MBBI, DL, get(Inst.getOpcode()), DstReg)
.addReg(SrcReg, getKillRegState(SrcReg != RISCV::X0))
.addReg(SrcReg, getKillRegState(SrcReg != RISCV::X0))
BuildMI(MBB, MBBI, DL, get(Inst.getOpcode()))
.addReg(DstReg, RegState::Define | DstRegState)
.addReg(SrcReg, SrcRegState)
.addReg(SrcReg, SrcRegState)
.setMIFlag(Flag);
break;
case RISCVMatInt::RegImm:
BuildMI(MBB, MBBI, DL, get(Inst.getOpcode()), DstReg)
.addReg(SrcReg, getKillRegState(SrcReg != RISCV::X0))
BuildMI(MBB, MBBI, DL, get(Inst.getOpcode()))
.addReg(DstReg, RegState::Define | DstRegState)
.addReg(SrcReg, SrcRegState)
.addImm(Inst.getImm())
.setMIFlag(Flag);
break;
}

// Only the first instruction has X0 as its source.
SrcReg = DstReg;
SrcRenamable = DstRenamable;
}
}

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3 changes: 2 additions & 1 deletion llvm/lib/Target/RISCV/RISCVInstrInfo.h
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Original file line number Diff line number Diff line change
Expand Up @@ -91,7 +91,8 @@ class RISCVInstrInfo : public RISCVGenInstrInfo {
// Materializes the given integer Val into DstReg.
void movImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
const DebugLoc &DL, Register DstReg, uint64_t Val,
MachineInstr::MIFlag Flag = MachineInstr::NoFlags) const;
MachineInstr::MIFlag Flag = MachineInstr::NoFlags,
bool DstRenamable = false, bool DstIsDead = false) const;

unsigned getInstSizeInBytes(const MachineInstr &MI) const override;

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47 changes: 4 additions & 43 deletions llvm/lib/Target/RISCV/RISCVPostRAExpandPseudoInsts.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -92,52 +92,13 @@ bool RISCVPostRAExpandPseudo::expandMovImm(MachineBasicBlock &MBB,
Val, MBB.getParent()->getSubtarget().getFeatureBits());
assert(!Seq.empty());

Register SrcReg = RISCV::X0;
Register DstReg = MBBI->getOperand(0).getReg();
bool DstIsDead = MBBI->getOperand(0).isDead();
bool Renamable = MBBI->getOperand(0).isRenamable();
bool SrcRenamable = false;
unsigned Num = 0;

for (RISCVMatInt::Inst &Inst : Seq) {
bool LastItem = ++Num == Seq.size();
switch (Inst.getOpndKind()) {
case RISCVMatInt::Imm:
BuildMI(MBB, MBBI, DL, TII->get(Inst.getOpcode()))
.addReg(DstReg, RegState::Define |
getDeadRegState(DstIsDead && LastItem) |
getRenamableRegState(Renamable))
.addImm(Inst.getImm());
break;
case RISCVMatInt::RegX0:
BuildMI(MBB, MBBI, DL, TII->get(Inst.getOpcode()))
.addReg(DstReg, RegState::Define |
getDeadRegState(DstIsDead && LastItem) |
getRenamableRegState(Renamable))
.addReg(SrcReg, RegState::Kill | getRenamableRegState(SrcRenamable))
.addReg(RISCV::X0);
break;
case RISCVMatInt::RegReg:
BuildMI(MBB, MBBI, DL, TII->get(Inst.getOpcode()))
.addReg(DstReg, RegState::Define |
getDeadRegState(DstIsDead && LastItem) |
getRenamableRegState(Renamable))
.addReg(SrcReg, RegState::Kill | getRenamableRegState(SrcRenamable))
.addReg(SrcReg, RegState::Kill | getRenamableRegState(SrcRenamable));
break;
case RISCVMatInt::RegImm:
BuildMI(MBB, MBBI, DL, TII->get(Inst.getOpcode()))
.addReg(DstReg, RegState::Define |
getDeadRegState(DstIsDead && LastItem) |
getRenamableRegState(Renamable))
.addReg(SrcReg, RegState::Kill | getRenamableRegState(SrcRenamable))
.addImm(Inst.getImm());
break;
}
// Only the first instruction has X0 as its source.
SrcReg = DstReg;
SrcRenamable = Renamable;
}

TII->movImm(MBB, MBBI, DL, DstReg, Val, MachineInstr::NoFlags, Renamable,
DstIsDead);

MBBI->eraseFromParent();
return true;
}
Expand Down