[RISCV] Add TuneVentanaVeyron subtarget feature.

[mgudim]

This will be used to add veyron fusions in a later commit.

[github-actions]

✅ With the latest revision this PR passed the C/C++ code formatter.

[llvmbot]

@llvm/pr-subscribers-backend-risc-v

Author: Mikhail Gudim (mgudim)

Changes

This will be used to add veyron fusions in a later commit.

---

Full diff: https://github.com/llvm/llvm-project/pull/70414.diff

3 Files Affected:

• (modified) llvm/lib/Target/RISCV/RISCVFeatures.td (+4)
• (modified) llvm/lib/Target/RISCV/RISCVProcessors.td (+2-1)
• (modified) llvm/lib/Target/RISCV/RISCVSubtarget.h (+1-4)

diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 979bc0ea8c7d065..ba6c63d8958e647 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -954,6 +954,10 @@ def TuneSiFive7 : SubtargetFeature<"sifive7", "RISCVProcFamily", "SiFive7",
                                    [TuneNoDefaultUnroll,
                                     TuneShortForwardBranchOpt]>;
 
+def TuneVentanaVeyron : SubtargetFeature<"ventana-veyron", "RISCVProcFamily", "VentanaVeyron",
+                                         "Ventana-Veyron Series processors",
+                                         [TuneLUIADDIFusion]>;
+
 // Assume that lock-free native-width atomics are available, even if the target
 // and operating system combination would not usually provide them. The user
 // is responsible for providing any necessary __sync implementations. Code
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
index e4008d145ffa572..5465e0c998ca6f8 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -242,4 +242,5 @@ def VENTANA_VEYRON_V1 : RISCVProcessorModel<"veyron-v1",
                                              FeatureStdExtZicbom,
                                              FeatureStdExtZicbop,
                                              FeatureStdExtZicboz,
-                                             FeatureVendorXVentanaCondOps]>;
+                                             FeatureVendorXVentanaCondOps],
+                                             [TuneVentanaVeyron]>;
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h
index 6b915e61c136086..4e84d7932c61c41 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -46,10 +46,7 @@ struct RISCVTuneInfo {
 
 class RISCVSubtarget : public RISCVGenSubtargetInfo {
 public:
-  enum RISCVProcFamilyEnum : uint8_t {
-    Others,
-    SiFive7,
-  };
+  enum RISCVProcFamilyEnum : uint8_t { Others, SiFive7, VentanaVeyron };
 
 private:
   virtual void anchor();

[topperc]

Please don't reformat this. I have other CPUs in this enum in my downstream. I'd prefer to keep one CPU per line. We can put a clang-format off/on around it.

[mgudim]

sure.

[topperc]

Leave a trailing comma after this. Makes it easier to insert new CPUs without touching this line.

[mgudim]

done

[topperc]

LGTM