Skip to content

[AMDGPU] Add option to pre-allocate SGPR spill VGPRs #70626

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 2 commits into from
Nov 13, 2023
Merged

[AMDGPU] Add option to pre-allocate SGPR spill VGPRs #70626

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
e25510b
[AMDGPU] Add option to pre-allocate SGPR spill VGPRs
perlfu Oct 30, 2023
29a24d9
Integrate with changes in moved WWM pre-allocation pass.
perlfu Nov 8, 2023
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
15 changes: 13 additions & 2 deletions llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -28,6 +28,10 @@ using namespace llvm;

#define DEBUG_TYPE "si-pre-allocate-wwm-regs"

static cl::opt<bool>
EnablePreallocateSGPRSpillVGPRs("amdgpu-prealloc-sgpr-spill-vgprs",
cl::init(false), cl::Hidden);

namespace {

class SIPreAllocateWWMRegs : public MachineFunctionPass {
Expand Down Expand Up @@ -199,6 +203,10 @@ bool SIPreAllocateWWMRegs::runOnMachineFunction(MachineFunction &MF) {

RegClassInfo.runOnMachineFunction(MF);

bool PreallocateSGPRSpillVGPRs =
EnablePreallocateSGPRSpillVGPRs ||
MF.getFunction().hasFnAttribute("amdgpu-prealloc-sgpr-spill-vgprs");
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Don't see why we would want this controllable by an attribute for migration purposes a flag is sufficient.

@cdevadas is also working on getting the proper allocator to handle the allocation of WWM registers

Copy link
Collaborator

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

For shaders, I hope the SGPR spills are very limited and they won't require more VGPRs causing the 'ran out of allocatable registers' error.

Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Don't see why we would want this controllable by an attribute for migration purposes a flag is sufficient.

For graphics we use the LLVM backed as a shared library so passing options into it via a command line argument (even if it's just for migration) is a terrible interface.

Copy link
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

As @jayfoad pointed out we typically use attributes as we can start embedding this in IR regardless of backend version.

I have spoken with @cdevadas about more complete allocator handling of WWM registers, and will support migration to it when from the graphics side when it is ready.

In the immediate term we need to work around corruption that split-spilling of SGPR spill VGPRs is causing (in complex divergent control flow) and can take the hit of pre-allocating the VGPRs required for all our current workloads.


bool RegsAssigned = false;

// We use a reverse post-order traversal of the control-flow graph to
Expand All @@ -215,8 +223,11 @@ bool SIPreAllocateWWMRegs::runOnMachineFunction(MachineFunction &MF) {
MI.getOpcode() == AMDGPU::V_SET_INACTIVE_B64)
RegsAssigned |= processDef(MI.getOperand(0));

if (MI.getOpcode() == AMDGPU::SI_SPILL_S32_TO_VGPR)
continue;
if (MI.getOpcode() == AMDGPU::SI_SPILL_S32_TO_VGPR) {
if (!PreallocateSGPRSpillVGPRs)
continue;
RegsAssigned |= processDef(MI.getOperand(0));
}

if (MI.getOpcode() == AMDGPU::ENTER_STRICT_WWM ||
MI.getOpcode() == AMDGPU::ENTER_STRICT_WQM ||
Expand Down
Loading