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[RISCV][NFC] Move getRVVMCOpcode to RISCVInstrInfo #70637

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Merged
merged 2 commits into from
Oct 30, 2023
Merged

[RISCV][NFC] Move getRVVMCOpcode to RISCVInstrInfo #70637

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92f381b
[RISCV][NFC] Move getRVVMCOpcode to RISCVInstrInfo
wangpc-pp Oct 30, 2023
b4df6ff
fixup! [RISCV][NFC] Move getRVVMCOpcode to RISCVInstrInfo
wangpc-pp Oct 30, 2023
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21 changes: 5 additions & 16 deletions llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2841,10 +2841,9 @@ bool RISCVDAGToDAGISel::selectSHXADD_UWOp(SDValue N, unsigned ShAmt,
static bool vectorPseudoHasAllNBitUsers(SDNode *User, unsigned UserOpNo,
unsigned Bits,
const TargetInstrInfo *TII) {
const RISCVVPseudosTable::PseudoInfo *PseudoInfo =
RISCVVPseudosTable::getPseudoInfo(User->getMachineOpcode());
unsigned MCOpcode = RISCV::getRVVMCOpcode(User->getMachineOpcode());

if (!PseudoInfo)
if (!MCOpcode)
return false;

const MCInstrDesc &MCID = TII->get(User->getMachineOpcode());
Expand All @@ -2865,7 +2864,7 @@ static bool vectorPseudoHasAllNBitUsers(SDNode *User, unsigned UserOpNo,
return false;

auto NumDemandedBits =
RISCV::getVectorLowDemandedScalarBits(PseudoInfo->BaseInstr, Log2SEW);
RISCV::getVectorLowDemandedScalarBits(MCOpcode, Log2SEW);
return NumDemandedBits && Bits >= *NumDemandedBits;
}

Expand Down Expand Up @@ -3404,21 +3403,11 @@ bool RISCVDAGToDAGISel::doPeepholeMaskedRVV(MachineSDNode *N) {
}

static bool IsVMerge(SDNode *N) {
unsigned Opc = N->getMachineOpcode();
return Opc == RISCV::PseudoVMERGE_VVM_MF8 ||
Opc == RISCV::PseudoVMERGE_VVM_MF4 ||
Opc == RISCV::PseudoVMERGE_VVM_MF2 ||
Opc == RISCV::PseudoVMERGE_VVM_M1 ||
Opc == RISCV::PseudoVMERGE_VVM_M2 ||
Opc == RISCV::PseudoVMERGE_VVM_M4 || Opc == RISCV::PseudoVMERGE_VVM_M8;
return RISCV::getRVVMCOpcode(N->getMachineOpcode()) == RISCV::VMERGE_VVM;
}

static bool IsVMv(SDNode *N) {
unsigned Opc = N->getMachineOpcode();
return Opc == RISCV::PseudoVMV_V_V_MF8 || Opc == RISCV::PseudoVMV_V_V_MF4 ||
Opc == RISCV::PseudoVMV_V_V_MF2 || Opc == RISCV::PseudoVMV_V_V_M1 ||
Opc == RISCV::PseudoVMV_V_V_M2 || Opc == RISCV::PseudoVMV_V_V_M4 ||
Opc == RISCV::PseudoVMV_V_V_M8;
return RISCV::getRVVMCOpcode(N->getMachineOpcode()) == RISCV::VMV_V_V;
}

static unsigned GetVMSetForLMul(RISCVII::VLMUL LMUL) {
Expand Down
20 changes: 6 additions & 14 deletions llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -67,16 +67,8 @@ static bool isVLPreservingConfig(const MachineInstr &MI) {
return RISCV::X0 == MI.getOperand(0).getReg();
}

static uint16_t getRVVMCOpcode(uint16_t RVVPseudoOpcode) {
const RISCVVPseudosTable::PseudoInfo *RVV =
RISCVVPseudosTable::getPseudoInfo(RVVPseudoOpcode);
if (!RVV)
return 0;
return RVV->BaseInstr;
}

static bool isFloatScalarMoveOrScalarSplatInstr(const MachineInstr &MI) {
switch (getRVVMCOpcode(MI.getOpcode())) {
switch (RISCV::getRVVMCOpcode(MI.getOpcode())) {
default:
return false;
case RISCV::VFMV_S_F:
Expand All @@ -86,7 +78,7 @@ static bool isFloatScalarMoveOrScalarSplatInstr(const MachineInstr &MI) {
}

static bool isScalarExtractInstr(const MachineInstr &MI) {
switch (getRVVMCOpcode(MI.getOpcode())) {
switch (RISCV::getRVVMCOpcode(MI.getOpcode())) {
default:
return false;
case RISCV::VMV_X_S:
Expand All @@ -96,7 +88,7 @@ static bool isScalarExtractInstr(const MachineInstr &MI) {
}

static bool isScalarInsertInstr(const MachineInstr &MI) {
switch (getRVVMCOpcode(MI.getOpcode())) {
switch (RISCV::getRVVMCOpcode(MI.getOpcode())) {
default:
return false;
case RISCV::VMV_S_X:
Expand All @@ -106,7 +98,7 @@ static bool isScalarInsertInstr(const MachineInstr &MI) {
}

static bool isScalarSplatInstr(const MachineInstr &MI) {
switch (getRVVMCOpcode(MI.getOpcode())) {
switch (RISCV::getRVVMCOpcode(MI.getOpcode())) {
default:
return false;
case RISCV::VMV_V_I:
Expand All @@ -117,7 +109,7 @@ static bool isScalarSplatInstr(const MachineInstr &MI) {
}

static bool isVSlideInstr(const MachineInstr &MI) {
switch (getRVVMCOpcode(MI.getOpcode())) {
switch (RISCV::getRVVMCOpcode(MI.getOpcode())) {
default:
return false;
case RISCV::VSLIDEDOWN_VX:
Expand All @@ -131,7 +123,7 @@ static bool isVSlideInstr(const MachineInstr &MI) {
/// Get the EEW for a load or store instruction. Return std::nullopt if MI is
/// not a load or store which ignores SEW.
static std::optional<unsigned> getEEWForLoadStore(const MachineInstr &MI) {
switch (getRVVMCOpcode(MI.getOpcode())) {
switch (RISCV::getRVVMCOpcode(MI.getOpcode())) {
default:
return std::nullopt;
case RISCV::VLE8_V:
Expand Down
8 changes: 8 additions & 0 deletions llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -3103,3 +3103,11 @@ RISCV::getVectorLowDemandedScalarBits(uint16_t Opcode, unsigned Log2SEW) {
return 1U << Log2SEW;
}
}

unsigned RISCV::getRVVMCOpcode(unsigned RVVPseudoOpcode) {
const RISCVVPseudosTable::PseudoInfo *RVV =
RISCVVPseudosTable::getPseudoInfo(RVVPseudoOpcode);
if (!RVV)
return 0;
return RVV->BaseInstr;
}
3 changes: 3 additions & 0 deletions llvm/lib/Target/RISCV/RISCVInstrInfo.h
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Original file line number Diff line number Diff line change
Expand Up @@ -283,6 +283,9 @@ bool hasEqualFRM(const MachineInstr &MI1, const MachineInstr &MI2);
std::optional<unsigned> getVectorLowDemandedScalarBits(uint16_t Opcode,
unsigned Log2SEW);

// Returns the MC opcode of RVV pseudo instruction.
unsigned getRVVMCOpcode(unsigned RVVPseudoOpcode);

// Special immediate for AVL operand of V pseudo instructions to indicate VLMax.
static constexpr int64_t VLMaxSentinel = -1LL;

Expand Down
7 changes: 3 additions & 4 deletions llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -84,10 +84,9 @@ FunctionPass *llvm::createRISCVOptWInstrsPass() {
static bool vectorPseudoHasAllNBitUsers(const MachineOperand &UserOp,
unsigned Bits) {
const MachineInstr &MI = *UserOp.getParent();
const RISCVVPseudosTable::PseudoInfo *PseudoInfo =
RISCVVPseudosTable::getPseudoInfo(MI.getOpcode());
unsigned MCOpcode = RISCV::getRVVMCOpcode(MI.getOpcode());

if (!PseudoInfo)
if (!MCOpcode)
return false;

const MCInstrDesc &MCID = MI.getDesc();
Expand All @@ -101,7 +100,7 @@ static bool vectorPseudoHasAllNBitUsers(const MachineOperand &UserOp,
return false;

auto NumDemandedBits =
RISCV::getVectorLowDemandedScalarBits(PseudoInfo->BaseInstr, Log2SEW);
RISCV::getVectorLowDemandedScalarBits(MCOpcode, Log2SEW);
return NumDemandedBits && Bits >= *NumDemandedBits;
}

Expand Down