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[X86][SDAG] Improve the lowering of s|uitofp i8|i16 to half #70834

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Merged
merged 2 commits into from
Nov 2, 2023
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[X86][SDAG] Improve the lowering of s|uitofp i8|i16 to half #70834

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c3d80cb
[X86][SDAG] Improve the lowering of `s|uitofp i8|i16 to half`
qcolombet Oct 31, 2023
4e1aab4
Use x86-64-v4 instead of specific CPU name
qcolombet Nov 1, 2023
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46 changes: 30 additions & 16 deletions llvm/lib/Target/X86/X86ISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -53390,19 +53390,26 @@ static SDValue combineUIntToFP(SDNode *N, SelectionDAG &DAG,
EVT VT = N->getValueType(0);
EVT InVT = Op0.getValueType();

// UINT_TO_FP(vXi1~15) -> UINT_TO_FP(ZEXT(vXi1~15 to vXi16))
// UINT_TO_FP(vXi17~31) -> UINT_TO_FP(ZEXT(vXi17~31 to vXi32))
// Using i16 as an intermediate type is a bad idea, unless we have HW support
// for it. Therefore for type sizes equal or smaller than 32 just go with i32.
// if hasFP16 support:
// UINT_TO_FP(vXi1~15) -> UINT_TO_FP(ZEXT(vXi1~15 to vXi16))
// UINT_TO_FP(vXi17~31) -> UINT_TO_FP(ZEXT(vXi17~31 to vXi32))
// else
// UINT_TO_FP(vXi1~31) -> UINT_TO_FP(ZEXT(vXi1~31 to vXi32))
// UINT_TO_FP(vXi33~63) -> UINT_TO_FP(ZEXT(vXi33~63 to vXi64))
if (InVT.isVector() && VT.getVectorElementType() == MVT::f16) {
unsigned ScalarSize = InVT.getScalarSizeInBits();
if (ScalarSize == 16 || ScalarSize == 32 || ScalarSize >= 64)
if ((ScalarSize == 16 && Subtarget.hasFP16()) || ScalarSize == 32 ||
ScalarSize >= 64)
return SDValue();
SDLoc dl(N);
EVT DstVT = EVT::getVectorVT(*DAG.getContext(),
ScalarSize < 16 ? MVT::i16
: ScalarSize < 32 ? MVT::i32
: MVT::i64,
InVT.getVectorNumElements());
EVT DstVT =
EVT::getVectorVT(*DAG.getContext(),
(Subtarget.hasFP16() && ScalarSize < 16) ? MVT::i16
: ScalarSize < 32 ? MVT::i32
: MVT::i64,
InVT.getVectorNumElements());
SDValue P = DAG.getNode(ISD::ZERO_EXTEND, dl, DstVT, Op0);
if (IsStrict)
return DAG.getNode(ISD::STRICT_UINT_TO_FP, dl, {VT, MVT::Other},
Expand Down Expand Up @@ -53453,19 +53460,26 @@ static SDValue combineSIntToFP(SDNode *N, SelectionDAG &DAG,
EVT VT = N->getValueType(0);
EVT InVT = Op0.getValueType();

// SINT_TO_FP(vXi1~15) -> SINT_TO_FP(SEXT(vXi1~15 to vXi16))
// SINT_TO_FP(vXi17~31) -> SINT_TO_FP(SEXT(vXi17~31 to vXi32))
// Using i16 as an intermediate type is a bad idea, unless we have HW support
// for it. Therefore for type sizes equal or smaller than 32 just go with i32.
// if hasFP16 support:
// SINT_TO_FP(vXi1~15) -> SINT_TO_FP(SEXT(vXi1~15 to vXi16))
// SINT_TO_FP(vXi17~31) -> SINT_TO_FP(SEXT(vXi17~31 to vXi32))
// else
// SINT_TO_FP(vXi1~31) -> SINT_TO_FP(ZEXT(vXi1~31 to vXi32))
// SINT_TO_FP(vXi33~63) -> SINT_TO_FP(SEXT(vXi33~63 to vXi64))
if (InVT.isVector() && VT.getVectorElementType() == MVT::f16) {
unsigned ScalarSize = InVT.getScalarSizeInBits();
if (ScalarSize == 16 || ScalarSize == 32 || ScalarSize >= 64)
if ((ScalarSize == 16 && Subtarget.hasFP16()) || ScalarSize == 32 ||
ScalarSize >= 64)
return SDValue();
SDLoc dl(N);
EVT DstVT = EVT::getVectorVT(*DAG.getContext(),
ScalarSize < 16 ? MVT::i16
: ScalarSize < 32 ? MVT::i32
: MVT::i64,
InVT.getVectorNumElements());
EVT DstVT =
EVT::getVectorVT(*DAG.getContext(),
(Subtarget.hasFP16() && ScalarSize < 16) ? MVT::i16
: ScalarSize < 32 ? MVT::i32
: MVT::i64,
InVT.getVectorNumElements());
SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
if (IsStrict)
return DAG.getNode(ISD::STRICT_SINT_TO_FP, dl, {VT, MVT::Other},
Expand Down
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