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[RISCV][GISel] Simplify selectSelect. NFC #70846

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Merged
merged 2 commits into from
Oct 31, 2023
Merged

[RISCV][GISel] Simplify selectSelect. NFC #70846

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9069bf9
[RISCV][GISel] Simplify selectSelect. NFC
topperc Oct 31, 2023
fbbd4c2
Fold mi_match into if
topperc Oct 31, 2023
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31 changes: 14 additions & 17 deletions llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -776,27 +776,24 @@ static void getICMPOperandsForBranch(MachineInstr &MI, MachineIRBuilder &MIB,
bool RISCVInstructionSelector::selectSelect(MachineInstr &MI,
MachineIRBuilder &MIB,
MachineRegisterInfo &MRI) const {
assert(MI.getOpcode() == TargetOpcode::G_SELECT);
auto &SelectMI = cast<GSelect>(MI);

// If MI is a G_SELECT(G_ICMP(tst, A, B), C, D) then we can use (A, B, tst)
// as the (LHS, RHS, CC) of the Select_GPR_Using_CC_GPR.
Register MIOp1Reg = MI.getOperand(1).getReg();
bool Op1IsICMP = mi_match(MIOp1Reg, MRI, m_GICmp(m_Pred(), m_Reg(), m_Reg()));
RISCVCC::CondCode CC;
Register LHS, RHS;
if (Op1IsICMP)
getICMPOperandsForBranch(*MRI.getVRegDef(MIOp1Reg), MIB, MRI, CC, LHS, RHS);

Register Op1 = Op1IsICMP ? LHS : MI.getOperand(1).getReg();
Register Op2 = Op1IsICMP ? RHS : RISCV::X0;
unsigned Op3 = Op1IsICMP ? CC : RISCVCC::COND_NE;
Register LHS = SelectMI.getCondReg();
Register RHS = RISCV::X0;
RISCVCC::CondCode CC = RISCVCC::COND_NE;

if (mi_match(LHS, MRI, m_GICmp(m_Pred(), m_Reg(), m_Reg())))
getICMPOperandsForBranch(*MRI.getVRegDef(LHS), MIB, MRI, CC, LHS, RHS);

MachineInstr *Result = MIB.buildInstr(RISCV::Select_GPR_Using_CC_GPR)
.addDef(MI.getOperand(0).getReg())
.addReg(Op1)
.addReg(Op2)
.addImm(Op3)
.addReg(MI.getOperand(2).getReg())
.addReg(MI.getOperand(3).getReg());
.addDef(SelectMI.getReg(0))
.addReg(LHS)
.addReg(RHS)
.addImm(CC)
.addReg(SelectMI.getTrueReg())
.addReg(SelectMI.getFalseReg());
MI.eraseFromParent();
return constrainSelectedInstRegOperands(*Result, TII, TRI, RBI);
}
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