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[RISCV] Remove experimental- prefix for smaia and ssaia. #71172

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Nov 4, 2023
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[RISCV] Remove experimental- prefix for smaia and ssaia. #71172

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71946ef
[RISCV] Remove experimental- prefix for smaia and ssaia.
Nov 3, 2023
f903839
Fix llvm/unittests/Support/RISCVISAInfoTest.cpp
Nov 3, 2023
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8 changes: 2 additions & 6 deletions llvm/docs/RISCVUsage.rst
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Expand Up @@ -90,6 +90,8 @@ on support follow.
``F`` Supported
``H`` Assembly Support
``M`` Supported
``Smaia`` Supported
``Ssaia`` Supported
``Svinval`` Assembly Support
``Svnapot`` Assembly Support
``Svpbmt`` Supported
Expand Down Expand Up @@ -188,12 +190,6 @@ LLVM supports (to various degrees) a number of experimental extensions. All exp

The primary goal of experimental support is to assist in the process of ratification by providing an existence proof of an implementation, and simplifying efforts to validate the value of a proposed extension against large code bases. Experimental extensions are expected to either transition to ratified status, or be eventually removed. The decision on whether to accept an experimental extension is currently done on an entirely case by case basis; if you want to propose one, attending the bi-weekly RISC-V sync-up call is strongly advised.

``experimental-smaia``
LLVM implements the `Ratification candidate 3 <https://github.com/riscv/riscv-aia/releases/tag/1.0-RC3>`_.

``experimental-ssaia``
LLVM implements the `Ratification candidate 3 <https://github.com/riscv/riscv-aia/releases/tag/1.0-RC3>`_.

``experimental-zacas``
LLVM implements the `1.0-rc1 draft specification <https://github.com/riscv/riscv-zacas/releases/tag/v1.0-rc1>`_.

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5 changes: 2 additions & 3 deletions llvm/lib/Support/RISCVISAInfo.cpp
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Expand Up @@ -59,6 +59,8 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
{"i", RISCVExtensionVersion{2, 1}},
{"m", RISCVExtensionVersion{2, 0}},

{"smaia", RISCVExtensionVersion{1, 0}},
{"ssaia", RISCVExtensionVersion{1, 0}},
{"svinval", RISCVExtensionVersion{1, 0}},
{"svnapot", RISCVExtensionVersion{1, 0}},
{"svpbmt", RISCVExtensionVersion{1, 0}},
Expand Down Expand Up @@ -166,9 +168,6 @@ static const RISCVSupportedExtension SupportedExtensions[] = {

// NOTE: This table should be sorted alphabetically by extension name.
static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
{"smaia", RISCVExtensionVersion{1, 0}},
{"ssaia", RISCVExtensionVersion{1, 0}},

{"zacas", RISCVExtensionVersion{1, 0}},

{"zfbfmin", RISCVExtensionVersion{0, 8}},
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4 changes: 2 additions & 2 deletions llvm/lib/Target/RISCV/RISCVFeatures.td
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Expand Up @@ -688,14 +688,14 @@ def HasStdExtZicond : Predicate<"Subtarget->hasStdExtZicond()">,
"'Zicond' (Integer Conditional Operations)">;

def FeatureStdExtSmaia
: SubtargetFeature<"experimental-smaia", "HasStdExtSmaia", "true",
: SubtargetFeature<"smaia", "HasStdExtSmaia", "true",
"'Smaia' (Smaia encompasses all added CSRs and all "
"modifications to interrupt response behavior that the "
"AIA specifies for a hart, over all privilege levels.)",
[]>;

def FeatureStdExtSsaia
: SubtargetFeature<"experimental-ssaia", "HasStdExtSsaia", "true",
: SubtargetFeature<"ssaia", "HasStdExtSsaia", "true",
"'Ssaia' (Ssaia is essentially the same as Smaia except "
"excluding the machine-level CSRs and behavior not "
"directly visible to supervisor level.)", []>;
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8 changes: 4 additions & 4 deletions llvm/test/CodeGen/RISCV/attributes.ll
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Expand Up @@ -81,8 +81,8 @@
; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvksh %s -o - | FileCheck --check-prefix=RV32ZVKSH %s
; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvkt %s -o - | FileCheck --check-prefix=RV32ZVKT %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zicond %s -o - | FileCheck --check-prefix=RV32ZICOND %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-smaia %s -o - | FileCheck --check-prefixes=CHECK,RV32SMAIA %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-ssaia %s -o - | FileCheck --check-prefixes=CHECK,RV32SSAIA %s
; RUN: llc -mtriple=riscv32 -mattr=+smaia %s -o - | FileCheck --check-prefixes=CHECK,RV32SMAIA %s
; RUN: llc -mtriple=riscv32 -mattr=+ssaia %s -o - | FileCheck --check-prefixes=CHECK,RV32SSAIA %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV32ZFBFMIN %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zvfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV32ZVFBFMIN %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zvfbfwma %s -o - | FileCheck --check-prefixes=CHECK,RV32ZVFBFWMA %s
Expand Down Expand Up @@ -171,8 +171,8 @@
; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvksh %s -o - | FileCheck --check-prefix=RV64ZVKSH %s
; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvkt %s -o - | FileCheck --check-prefix=RV64ZVKT %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zicond %s -o - | FileCheck --check-prefix=RV64ZICOND %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-smaia %s -o - | FileCheck --check-prefixes=CHECK,RV64SMAIA %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-ssaia %s -o - | FileCheck --check-prefixes=CHECK,RV64SSAIA %s
; RUN: llc -mtriple=riscv64 -mattr=+smaia %s -o - | FileCheck --check-prefixes=CHECK,RV64SMAIA %s
; RUN: llc -mtriple=riscv64 -mattr=+ssaia %s -o - | FileCheck --check-prefixes=CHECK,RV64SSAIA %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV64ZFBFMIN %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zvfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV64ZVFBFMIN %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zvfbfwma %s -o - | FileCheck --check-prefixes=CHECK,RV64ZVFBFWMA %s
Expand Down
4 changes: 2 additions & 2 deletions llvm/unittests/Support/RISCVISAInfoTest.cpp
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Expand Up @@ -704,6 +704,8 @@ R"(All available -march extensions for RISC-V
zvl8192b 1.0
zhinx 1.0
zhinxmin 1.0
smaia 1.0
ssaia 1.0
svinval 1.0
svnapot 1.0
svpbmt 1.0
Expand Down Expand Up @@ -755,8 +757,6 @@ Experimental extensions
zvksg 1.0
zvksh 1.0
zvkt 1.0
smaia 1.0
ssaia 1.0

Use -march to specify the target's extension.
For example, clang -march=rv32i_v1p0)";
Expand Down