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[RISCVInsertVSETVLI] Allow PRE with non-immediate AVLs #71728

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Nov 9, 2023
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[RISCVInsertVSETVLI] Allow PRE with non-immediate AVLs #71728

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[RISCVInsertVSETVLI] Allow PRE with non-immediate AVLs
preames Nov 8, 2023
a973333
Update llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
preames Nov 9, 2023
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41 changes: 15 additions & 26 deletions llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1308,29 +1308,6 @@ void RISCVInsertVSETVLI::emitVSETVLIs(MachineBasicBlock &MBB) {
}
}

/// Return true if the VL value configured by a vset(i)vli with the
/// provided Info must be equal to the requested AVL. That is, that
/// AVL <= VLMAX.
static bool willVLBeAVL(const VSETVLIInfo &Info, const RISCVSubtarget &ST) {
if (!Info.hasAVLImm())
// VLMAX is always the same value.
// TODO: Could extend to other registers by looking at the associated vreg
// def placement.
return RISCV::X0 == Info.getAVLReg();

unsigned AVL = Info.getAVLImm();
unsigned SEW = Info.getSEW();
unsigned AVLInBits = AVL * SEW;

unsigned LMul;
bool Fractional;
std::tie(LMul, Fractional) = RISCVVType::decodeVLMUL(Info.getVLMUL());

if (Fractional)
return ST.getRealMinVLen() / LMul >= AVLInBits;
return ST.getRealMinVLen() * LMul >= AVLInBits;
}

/// Perform simple partial redundancy elimination of the VSETVLI instructions
/// we're about to insert by looking for cases where we can PRE from the
/// beginning of one block to the end of one of its predecessors. Specifically,
Expand Down Expand Up @@ -1364,9 +1341,21 @@ void RISCVInsertVSETVLI::doPRE(MachineBasicBlock &MBB) {
if (UnavailablePred->succ_size() != 1)
return;

// If VL can be less than AVL, then we can't reduce the frequency of exec.
if (!willVLBeAVL(AvailableInfo, *ST))
return;
// If the AVL value is a register (other than our VLMAX sentinel),
// we need to prove the value is available at the point we're going
// to insert the vsetvli at.
if (AvailableInfo.hasAVLReg() && RISCV::X0 != AvailableInfo.getAVLReg()) {
MachineInstr *AVLDefMI = MRI->getVRegDef(AvailableInfo.getAVLReg());
if (!AVLDefMI)
return;
// This is an inline dominance check which covers the case of
// UnavailablePred being the preheader of a loop.
if (AVLDefMI->getParent() != UnavailablePred)
return;
for (auto &TermMI : UnavailablePred->terminators())
if (&TermMI == AVLDefMI)
return;
}

// Model the effect of changing the input state of the block MBB to
// AvailableInfo. We're looking for two issues here; one legality,
Expand Down
56 changes: 28 additions & 28 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-store-asm.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -14,12 +14,12 @@ define void @gather(ptr noalias nocapture %A, ptr noalias nocapture readonly %B)
; CHECK-LABEL: gather:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: li a2, 1024
; CHECK-NEXT: li a3, 32
; CHECK-NEXT: li a4, 5
; CHECK-NEXT: li a4, 32
; CHECK-NEXT: li a3, 5
; CHECK-NEXT: vsetvli zero, a4, e8, m1, ta, ma
; CHECK-NEXT: .LBB0_1: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vsetvli zero, a3, e8, m1, ta, ma
; CHECK-NEXT: vlse8.v v8, (a1), a4
; CHECK-NEXT: vlse8.v v8, (a1), a3
; CHECK-NEXT: vle8.v v9, (a0)
; CHECK-NEXT: vadd.vv v8, v9, v8
; CHECK-NEXT: vse8.v v8, (a0)
Expand Down Expand Up @@ -126,12 +126,12 @@ define void @gather_negative_stride(ptr noalias nocapture %A, ptr noalias nocapt
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi a1, a1, 155
; CHECK-NEXT: li a2, 1024
; CHECK-NEXT: li a3, 32
; CHECK-NEXT: li a4, -5
; CHECK-NEXT: li a4, 32
; CHECK-NEXT: li a3, -5
; CHECK-NEXT: vsetvli zero, a4, e8, m1, ta, ma
; CHECK-NEXT: .LBB2_1: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vsetvli zero, a3, e8, m1, ta, ma
; CHECK-NEXT: vlse8.v v8, (a1), a4
; CHECK-NEXT: vlse8.v v8, (a1), a3
; CHECK-NEXT: vle8.v v9, (a0)
; CHECK-NEXT: vadd.vv v8, v9, v8
; CHECK-NEXT: vse8.v v8, (a0)
Expand Down Expand Up @@ -168,12 +168,12 @@ define void @gather_zero_stride(ptr noalias nocapture %A, ptr noalias nocapture
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: li a2, 1024
; CHECK-NEXT: li a3, 32
; CHECK-NEXT: vsetvli zero, a3, e8, m1, ta, ma
; CHECK-NEXT: .LBB3_1: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: lbu a4, 0(a1)
; CHECK-NEXT: vsetvli zero, a3, e8, m1, ta, ma
; CHECK-NEXT: lbu a3, 0(a1)
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vadd.vx v8, v8, a4
; CHECK-NEXT: vadd.vx v8, v8, a3
; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: addi a2, a2, -32
; CHECK-NEXT: addi a0, a0, 32
Expand Down Expand Up @@ -208,9 +208,9 @@ define void @gather_zero_stride_unfold(ptr noalias nocapture %A, ptr noalias noc
; V: # %bb.0: # %entry
; V-NEXT: li a2, 1024
; V-NEXT: li a3, 32
; V-NEXT: vsetvli zero, a3, e8, m1, ta, ma
; V-NEXT: .LBB4_1: # %vector.body
; V-NEXT: # =>This Inner Loop Header: Depth=1
; V-NEXT: vsetvli zero, a3, e8, m1, ta, ma
; V-NEXT: vlse8.v v8, (a1), zero
; V-NEXT: vle8.v v9, (a0)
; V-NEXT: vdivu.vv v8, v8, v9
Expand All @@ -226,9 +226,9 @@ define void @gather_zero_stride_unfold(ptr noalias nocapture %A, ptr noalias noc
; ZVE32F: # %bb.0: # %entry
; ZVE32F-NEXT: li a2, 1024
; ZVE32F-NEXT: li a3, 32
; ZVE32F-NEXT: vsetvli zero, a3, e8, m1, ta, ma
; ZVE32F-NEXT: .LBB4_1: # %vector.body
; ZVE32F-NEXT: # =>This Inner Loop Header: Depth=1
; ZVE32F-NEXT: vsetvli zero, a3, e8, m1, ta, ma
; ZVE32F-NEXT: vlse8.v v8, (a1), zero
; ZVE32F-NEXT: vle8.v v9, (a0)
; ZVE32F-NEXT: vdivu.vv v8, v8, v9
Expand All @@ -244,12 +244,12 @@ define void @gather_zero_stride_unfold(ptr noalias nocapture %A, ptr noalias noc
; NOT-OPTIMIZED: # %bb.0: # %entry
; NOT-OPTIMIZED-NEXT: li a2, 1024
; NOT-OPTIMIZED-NEXT: li a3, 32
; NOT-OPTIMIZED-NEXT: vsetvli zero, a3, e8, m1, ta, ma
; NOT-OPTIMIZED-NEXT: .LBB4_1: # %vector.body
; NOT-OPTIMIZED-NEXT: # =>This Inner Loop Header: Depth=1
; NOT-OPTIMIZED-NEXT: lbu a4, 0(a1)
; NOT-OPTIMIZED-NEXT: vsetvli zero, a3, e8, m1, ta, ma
; NOT-OPTIMIZED-NEXT: lbu a3, 0(a1)
; NOT-OPTIMIZED-NEXT: vle8.v v8, (a0)
; NOT-OPTIMIZED-NEXT: vmv.v.x v9, a4
; NOT-OPTIMIZED-NEXT: vmv.v.x v9, a3
; NOT-OPTIMIZED-NEXT: vdivu.vv v8, v9, v8
; NOT-OPTIMIZED-NEXT: vse8.v v8, (a0)
; NOT-OPTIMIZED-NEXT: addi a2, a2, -32
Expand Down Expand Up @@ -288,15 +288,15 @@ define void @scatter(ptr noalias nocapture %A, ptr noalias nocapture readonly %B
; CHECK-LABEL: scatter:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: li a2, 1024
; CHECK-NEXT: li a3, 32
; CHECK-NEXT: li a4, 5
; CHECK-NEXT: li a4, 32
; CHECK-NEXT: li a3, 5
; CHECK-NEXT: vsetvli zero, a4, e8, m1, ta, ma
; CHECK-NEXT: .LBB5_1: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vsetvli zero, a3, e8, m1, ta, ma
; CHECK-NEXT: vle8.v v8, (a1)
; CHECK-NEXT: vlse8.v v9, (a0), a4
; CHECK-NEXT: vlse8.v v9, (a0), a3
; CHECK-NEXT: vadd.vv v8, v9, v8
; CHECK-NEXT: vsse8.v v8, (a0), a4
; CHECK-NEXT: vsse8.v v8, (a0), a3
; CHECK-NEXT: addi a2, a2, -32
; CHECK-NEXT: addi a1, a1, 32
; CHECK-NEXT: addi a0, a0, 160
Expand Down Expand Up @@ -821,20 +821,20 @@ define void @strided_load_startval_add_with_splat(ptr noalias nocapture %arg, pt
; CHECK-NEXT: add a6, a0, a2
; CHECK-NEXT: add a2, a1, a2
; CHECK-NEXT: add a2, a2, a7
; CHECK-NEXT: li a7, 32
; CHECK-NEXT: li t0, 5
; CHECK-NEXT: mv t1, a5
; CHECK-NEXT: li t0, 32
; CHECK-NEXT: li a7, 5
; CHECK-NEXT: vsetvli zero, t0, e8, m1, ta, ma
; CHECK-NEXT: mv t0, a5
; CHECK-NEXT: .LBB13_3: # %bb15
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vsetvli zero, a7, e8, m1, ta, ma
; CHECK-NEXT: vlse8.v v8, (a2), t0
; CHECK-NEXT: vlse8.v v8, (a2), a7
; CHECK-NEXT: vle8.v v9, (a6)
; CHECK-NEXT: vadd.vv v8, v9, v8
; CHECK-NEXT: vse8.v v8, (a6)
; CHECK-NEXT: addi t1, t1, -32
; CHECK-NEXT: addi t0, t0, -32
; CHECK-NEXT: addi a6, a6, 32
; CHECK-NEXT: addi a2, a2, 160
; CHECK-NEXT: bnez t1, .LBB13_3
; CHECK-NEXT: bnez t0, .LBB13_3
; CHECK-NEXT: # %bb.4: # %bb30
; CHECK-NEXT: beq a4, a5, .LBB13_7
; CHECK-NEXT: .LBB13_5: # %bb32
Expand Down
14 changes: 7 additions & 7 deletions llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -3892,9 +3892,9 @@ define void @sink_splat_mul_lmul8(ptr nocapture %a, i32 signext %x) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: li a2, 1024
; CHECK-NEXT: li a3, 32
; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; CHECK-NEXT: .LBB74_1: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vmul.vx v8, v8, a1
; CHECK-NEXT: vse32.v v8, (a0)
Expand Down Expand Up @@ -3927,9 +3927,9 @@ define void @sink_splat_add_lmul8(ptr nocapture %a, i32 signext %x) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: li a2, 1024
; CHECK-NEXT: li a3, 32
; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; CHECK-NEXT: .LBB75_1: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vadd.vx v8, v8, a1
; CHECK-NEXT: vse32.v v8, (a0)
Expand Down Expand Up @@ -3962,9 +3962,9 @@ define void @sink_splat_sub_lmul8(ptr nocapture %a, i32 signext %x) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: li a2, 1024
; CHECK-NEXT: li a3, 32
; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; CHECK-NEXT: .LBB76_1: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsub.vx v8, v8, a1
; CHECK-NEXT: vse32.v v8, (a0)
Expand Down Expand Up @@ -3997,9 +3997,9 @@ define void @sink_splat_rsub_lmul8(ptr nocapture %a, i32 signext %x) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: li a2, 1024
; CHECK-NEXT: li a3, 32
; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; CHECK-NEXT: .LBB77_1: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vrsub.vx v8, v8, a1
; CHECK-NEXT: vse32.v v8, (a0)
Expand Down Expand Up @@ -4032,9 +4032,9 @@ define void @sink_splat_and_lmul8(ptr nocapture %a, i32 signext %x) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: li a2, 1024
; CHECK-NEXT: li a3, 32
; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; CHECK-NEXT: .LBB78_1: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vand.vx v8, v8, a1
; CHECK-NEXT: vse32.v v8, (a0)
Expand Down Expand Up @@ -4067,9 +4067,9 @@ define void @sink_splat_or_lmul8(ptr nocapture %a, i32 signext %x) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: li a2, 1024
; CHECK-NEXT: li a3, 32
; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; CHECK-NEXT: .LBB79_1: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vor.vx v8, v8, a1
; CHECK-NEXT: vse32.v v8, (a0)
Expand Down Expand Up @@ -4102,9 +4102,9 @@ define void @sink_splat_xor_lmul8(ptr nocapture %a, i32 signext %x) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: li a2, 1024
; CHECK-NEXT: li a3, 32
; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; CHECK-NEXT: .LBB80_1: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vxor.vx v8, v8, a1
; CHECK-NEXT: vse32.v v8, (a0)
Expand Down