[lldb][AArch64][Linux] Add field information for the mte_ctrl register

lldb/packages/Python/lldbsuite/test/lldbtest.py

@@ -1224,6 +1224,17 @@ def dumpSessionInfo(self):
     # (enables reading of the current test configuration)
     # ====================================================
 
+    def hasXMLSupport(self):
+        """Returns True if lldb was built with XML support. Use this check to
+        enable parts of tests, if you want to skip a whole test use skipIfXmlSupportMissing
+        instead."""
+        return (
+            lldb.SBDebugger.GetBuildConfiguration()
+            .GetValueForKey("xml")
+            .GetValueForKey("value")
+            .GetBooleanValue(False)
+        )
+
     def isMIPS(self):
         """Returns true if the architecture is MIPS."""
         arch = self.getArchitecture()

lldb/source/Plugins/Process/Utility/RegisterFlagsLinux_arm64.cpp

@@ -24,6 +24,19 @@
 
 using namespace lldb_private;
 
+LinuxArm64RegisterFlags::Fields
+LinuxArm64RegisterFlags::DetectMTECtrlFields(uint64_t hwcap, uint64_t hwcap2) {
+  (void)hwcap;
+  (void)hwcap2;
+  // Represents the contents of NT_ARM_TAGGED_ADDR_CTRL and the value passed
+  // to prctl(PR_TAGGED_ADDR_CTRL...). Fields are derived from the defines
+  // used to build the value.
+  return {{"TAGS", 3, 18}, // 16 bit bitfield shifted up by PR_MTE_TAG_SHIFT.
+          {"TCF_ASYNC", 2},
+          {"TCF_SYNC", 1},
+          {"TAGGED_ADDR_ENABLE", 0}};
+}
+
 LinuxArm64RegisterFlags::Fields
 LinuxArm64RegisterFlags::DetectFPCRFields(uint64_t hwcap, uint64_t hwcap2) {
   std::vector<RegisterFlags::Field> fpcr_fields{

lldb/source/Plugins/Process/Utility/RegisterFlagsLinux_arm64.h

@@ -58,6 +58,7 @@ class LinuxArm64RegisterFlags {
   static Fields DetectCPSRFields(uint64_t hwcap, uint64_t hwcap2);
   static Fields DetectFPSRFields(uint64_t hwcap, uint64_t hwcap2);
   static Fields DetectFPCRFields(uint64_t hwcap, uint64_t hwcap2);
+  static Fields DetectMTECtrlFields(uint64_t hwcap, uint64_t hwcap2);
 
   struct RegisterEntry {
     RegisterEntry(llvm::StringRef name, unsigned size, DetectorFn detector)
@@ -67,10 +68,11 @@ class LinuxArm64RegisterFlags {
     llvm::StringRef m_name;
     RegisterFlags m_flags;
     DetectorFn m_detector;
-  } m_registers[3] = {
+  } m_registers[4] = {
       RegisterEntry("cpsr", 4, DetectCPSRFields),
       RegisterEntry("fpsr", 4, DetectFPSRFields),
       RegisterEntry("fpcr", 4, DetectFPCRFields),
+      RegisterEntry("mte_ctrl", 8, DetectMTECtrlFields),
   };
 
   // Becomes true once field detection has been run for all registers.

lldb/test/API/commands/register/register/aarch64_mte_ctrl_register/TestMTECtrlRegister.py

@@ -34,17 +34,28 @@ def test_mte_ctrl_register(self):
             substrs=["stop reason = breakpoint 1."],
         )
 
-        # Bit 0 = tagged addressing enabled
-        # Bit 1 = synchronous faults
-        # Bit 2 = asynchronous faults
-        # We start enabled with synchronous faults.
-        self.expect("register read mte_ctrl", substrs=["0x0000000000000003"])
+        def check_mte_ctrl(async_err, sync_err):
+            # Bit 0 = tagged addressing enabled
+            # Bit 1 = synchronous faults
+            # Bit 2 = asynchronous faults
+            value = "0x{:016x}".format((async_err << 2) | (sync_err << 1) | 1)
+            expected = [value]
+
+            if self.hasXMLSupport():
+                expected.append(
+                    "(TAGS = 0, TCF_ASYNC = {}, TCF_SYNC = {}, TAGGED_ADDR_ENABLE = 1)".format(
+                        async_err, sync_err
+                    )
+                )
+
+            self.expect("register read mte_ctrl", substrs=expected)
 
+        # We start enabled with synchronous faults.
+        check_mte_ctrl(0, 1)
         # Change to asynchronous faults.
         self.runCmd("register write mte_ctrl 5")
-        self.expect("register read mte_ctrl", substrs=["0x0000000000000005"])
-
+        check_mte_ctrl(1, 0)
         # This would return to synchronous faults if we did not restore the
         # previous value.
         self.expect("expression setup_mte()", substrs=["= 0"])
-        self.expect("register read mte_ctrl", substrs=["0x0000000000000005"])
+        check_mte_ctrl(1, 0)

lldb/test/API/linux/aarch64/mte_core_file/TestAArch64LinuxMTEMemoryTagCoreFile.py

@@ -235,4 +235,11 @@ def test_mte_ctrl_register(self):
         # * Allowed tags value of 0xFFFF, shifted up by 3 resulting in 0x7fff8.
         # * Bit 1 set to enable synchronous tag faults.
         # * Bit 0 set to enable the tagged address ABI.
-        self.expect("register read mte_ctrl", substrs=["mte_ctrl = 0x000000000007fffb"])
+        expected = ["mte_ctrl = 0x000000000007fffb"]
+
+        if self.hasXMLSupport():
+            expected.append(
+                "(TAGS = 65535, TCF_ASYNC = 0, TCF_SYNC = 1, TAGGED_ADDR_ENABLE = 1)"
+            )
+
+        self.expect("register read mte_ctrl", substrs=expected)