Skip to content

[InstCombine] Infer zext nneg flag directly #71906

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Closed
wants to merge 1 commit into from
Closed

[InstCombine] Infer zext nneg flag directly #71906

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
8 changes: 6 additions & 2 deletions llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -542,7 +542,8 @@ static Instruction *foldCttzCtlz(IntrinsicInst &II, InstCombinerImpl &IC) {
if (match(Op0, m_OneUse(m_ZExt(m_Value(X)))) && match(Op1, m_One())) {
auto *Cttz = IC.Builder.CreateBinaryIntrinsic(Intrinsic::cttz, X,
IC.Builder.getTrue());
auto *ZextCttz = IC.Builder.CreateZExt(Cttz, II.getType());
auto *ZextCttz = IC.Builder.CreateZExt(Cttz, II.getType(), /*Name*/ "",
/*IsNonNeg*/ true);
return IC.replaceInstUsesWith(II, ZextCttz);
}

Expand Down Expand Up @@ -639,7 +640,10 @@ static Instruction *foldCtpop(IntrinsicInst &II, InstCombinerImpl &IC) {
// ctpop (zext X) --> zext (ctpop X)
if (match(Op0, m_OneUse(m_ZExt(m_Value(X))))) {
Value *NarrowPop = IC.Builder.CreateUnaryIntrinsic(Intrinsic::ctpop, X);
return CastInst::Create(Instruction::ZExt, NarrowPop, Ty);
Instruction *Zext = CastInst::Create(Instruction::ZExt, NarrowPop, Ty);
if (X->getType()->getScalarSizeInBits() > 2)
Zext->setNonNeg();
return Zext;
}

KnownBits Known(BitWidth);
Expand Down
4 changes: 3 additions & 1 deletion llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1159,7 +1159,9 @@ Instruction *InstCombinerImpl::visitZExt(ZExtInst &Zext) {
APInt AndValue(APInt::getLowBitsSet(SrcSize, MidSize));
Constant *AndConst = ConstantInt::get(A->getType(), AndValue);
Value *And = Builder.CreateAnd(A, AndConst, CSrc->getName() + ".mask");
return new ZExtInst(And, DestTy);
auto *ZExt = new ZExtInst(And, DestTy);
ZExt->setNonNeg();
return ZExt;
}

if (SrcSize == DstSize) {
Expand Down
4 changes: 3 additions & 1 deletion llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -5913,7 +5913,9 @@ static Instruction *processUMulZExtIdiom(ICmpInst &I, Value *MulVal,
ConstantInt *CI = cast<ConstantInt>(BO->getOperand(1));
APInt ShortMask = CI->getValue().trunc(MulWidth);
Value *ShortAnd = Builder.CreateAnd(Mul, ShortMask);
Value *Zext = Builder.CreateZExt(ShortAnd, BO->getType());
Value *Zext =
Builder.CreateZExt(ShortAnd, BO->getType(), /*Name*/ "",
/*IsNonNeg*/ ShortMask.isNonNegative());
IC.replaceInstUsesWith(*BO, Zext);
} else {
llvm_unreachable("Unexpected Binary operation");
Expand Down
5 changes: 4 additions & 1 deletion llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1243,7 +1243,10 @@ static Value *takeLog2(IRBuilderBase &Builder, Value *Op, unsigned Depth,
Value *X, *Y;
if (match(Op, m_ZExt(m_Value(X))))
if (Value *LogX = takeLog2(Builder, X, Depth, AssumeNonZero, DoFold))
return IfFold([&]() { return Builder.CreateZExt(LogX, Op->getType()); });
return IfFold([&]() {
return Builder.CreateZExt(LogX, Op->getType(), /*Name*/ "",
/*IsNonNeg*/ true);
});

// log2(X << Y) -> log2(X) + Y
// FIXME: Require one use unless X is 1?
Expand Down
12 changes: 9 additions & 3 deletions llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -408,7 +408,8 @@ Instruction *InstCombinerImpl::commonShiftTransforms(BinaryOperator &I) {
// If the shift amount is a one-use `sext`, we can demote it to `zext`.
Value *Y;
if (match(Op1, m_OneUse(m_SExt(m_Value(Y))))) {
Value *NewExt = Builder.CreateZExt(Y, Ty, Op1->getName());
Value *NewExt =
Builder.CreateZExt(Y, Ty, Op1->getName(), /*IsNonNeg*/ true);
return BinaryOperator::Create(I.getOpcode(), Op0, NewExt);
}

Expand Down Expand Up @@ -1331,7 +1332,10 @@ Instruction *InstCombinerImpl::visitLShr(BinaryOperator &I) {
"Big shift not simplified to zero?");
// lshr (zext iM X to iN), C --> zext (lshr X, C) to iN
Value *NewLShr = Builder.CreateLShr(X, ShAmtC);
return new ZExtInst(NewLShr, Ty);
auto *Zext = new ZExtInst(NewLShr, Ty);
if (ShAmtC)
Zext->setNonNeg();
return Zext;
}

if (match(Op0, m_SExt(m_Value(X)))) {
Expand All @@ -1349,7 +1353,9 @@ Instruction *InstCombinerImpl::visitLShr(BinaryOperator &I) {
// zeros? lshr (sext iM X to iN), N-1 --> zext (lshr X, M-1) to iN
if (ShAmtC == BitWidth - 1) {
Value *NewLShr = Builder.CreateLShr(X, SrcTyBitWidth - 1);
return new ZExtInst(NewLShr, Ty);
auto *Zext = new ZExtInst(NewLShr, Ty);
Zext->setNonNeg();
return Zext;
}

// lshr (sext iM X to iN), N-M --> zext (ashr X, min(N-M, M-1)) to iN
Expand Down
2 changes: 2 additions & 0 deletions llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -481,6 +481,8 @@ Value *InstCombinerImpl::SimplifyDemandedUseBits(Value *V, APInt DemandedMask,
DemandedMask.getActiveBits() <= SrcBitWidth) {
// Convert to ZExt cast.
CastInst *NewCast = new ZExtInst(I->getOperand(0), VTy, I->getName());
if (InputKnown.isNonNegative())
NewCast->setNonNeg();
return InsertNewInstWith(NewCast, I->getIterator());
}

Expand Down
4 changes: 2 additions & 2 deletions llvm/test/Transforms/InstCombine/div-shift.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -38,7 +38,7 @@ define <2 x i32> @t1vec(<2 x i16> %x, <2 x i32> %y) {
; rdar://11721329
define i64 @t2(i64 %x, i32 %y) {
; CHECK-LABEL: @t2(
; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[Y:%.*]] to i64
; CHECK-NEXT: [[TMP1:%.*]] = zext nneg i32 [[Y:%.*]] to i64
; CHECK-NEXT: [[TMP2:%.*]] = lshr i64 [[X:%.*]], [[TMP1]]
; CHECK-NEXT: ret i64 [[TMP2]]
;
Expand All @@ -52,7 +52,7 @@ define i64 @t2(i64 %x, i32 %y) {
define i64 @t3(i64 %x, i32 %y) {
; CHECK-LABEL: @t3(
; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[Y:%.*]], 2
; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
; CHECK-NEXT: [[TMP2:%.*]] = zext nneg i32 [[TMP1]] to i64
; CHECK-NEXT: [[TMP3:%.*]] = lshr i64 [[X:%.*]], [[TMP2]]
; CHECK-NEXT: ret i64 [[TMP3]]
;
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/Transforms/InstCombine/load-cmp.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -122,7 +122,7 @@ define i1 @test4(i32 %X) {

define i1 @test4_i16(i16 %X) {
; CHECK-LABEL: @test4_i16(
; CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[X:%.*]] to i32
; CHECK-NEXT: [[TMP1:%.*]] = zext nneg i16 [[X:%.*]] to i32
; CHECK-NEXT: [[TMP2:%.*]] = lshr i32 933, [[TMP1]]
; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[TMP2]], 1
; CHECK-NEXT: [[R:%.*]] = icmp ne i32 [[TMP3]], 0
Expand Down
12 changes: 6 additions & 6 deletions llvm/test/Transforms/InstCombine/shift-by-signext.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -6,7 +6,7 @@

define i32 @t0_shl(i32 %x, i8 %shamt) {
; CHECK-LABEL: @t0_shl(
; CHECK-NEXT: [[SHAMT_WIDE1:%.*]] = zext i8 [[SHAMT:%.*]] to i32
; CHECK-NEXT: [[SHAMT_WIDE1:%.*]] = zext nneg i8 [[SHAMT:%.*]] to i32
; CHECK-NEXT: [[R:%.*]] = shl i32 [[X:%.*]], [[SHAMT_WIDE1]]
; CHECK-NEXT: ret i32 [[R]]
;
Expand All @@ -16,7 +16,7 @@ define i32 @t0_shl(i32 %x, i8 %shamt) {
}
define i32 @t1_lshr(i32 %x, i8 %shamt) {
; CHECK-LABEL: @t1_lshr(
; CHECK-NEXT: [[SHAMT_WIDE1:%.*]] = zext i8 [[SHAMT:%.*]] to i32
; CHECK-NEXT: [[SHAMT_WIDE1:%.*]] = zext nneg i8 [[SHAMT:%.*]] to i32
; CHECK-NEXT: [[R:%.*]] = lshr i32 [[X:%.*]], [[SHAMT_WIDE1]]
; CHECK-NEXT: ret i32 [[R]]
;
Expand All @@ -26,7 +26,7 @@ define i32 @t1_lshr(i32 %x, i8 %shamt) {
}
define i32 @t2_ashr(i32 %x, i8 %shamt) {
; CHECK-LABEL: @t2_ashr(
; CHECK-NEXT: [[SHAMT_WIDE1:%.*]] = zext i8 [[SHAMT:%.*]] to i32
; CHECK-NEXT: [[SHAMT_WIDE1:%.*]] = zext nneg i8 [[SHAMT:%.*]] to i32
; CHECK-NEXT: [[R:%.*]] = ashr i32 [[X:%.*]], [[SHAMT_WIDE1]]
; CHECK-NEXT: ret i32 [[R]]
;
Expand All @@ -37,7 +37,7 @@ define i32 @t2_ashr(i32 %x, i8 %shamt) {

define <2 x i32> @t3_vec_shl(<2 x i32> %x, <2 x i8> %shamt) {
; CHECK-LABEL: @t3_vec_shl(
; CHECK-NEXT: [[SHAMT_WIDE1:%.*]] = zext <2 x i8> [[SHAMT:%.*]] to <2 x i32>
; CHECK-NEXT: [[SHAMT_WIDE1:%.*]] = zext nneg <2 x i8> [[SHAMT:%.*]] to <2 x i32>
; CHECK-NEXT: [[R:%.*]] = shl <2 x i32> [[X:%.*]], [[SHAMT_WIDE1]]
; CHECK-NEXT: ret <2 x i32> [[R]]
;
Expand All @@ -47,7 +47,7 @@ define <2 x i32> @t3_vec_shl(<2 x i32> %x, <2 x i8> %shamt) {
}
define <2 x i32> @t4_vec_lshr(<2 x i32> %x, <2 x i8> %shamt) {
; CHECK-LABEL: @t4_vec_lshr(
; CHECK-NEXT: [[SHAMT_WIDE1:%.*]] = zext <2 x i8> [[SHAMT:%.*]] to <2 x i32>
; CHECK-NEXT: [[SHAMT_WIDE1:%.*]] = zext nneg <2 x i8> [[SHAMT:%.*]] to <2 x i32>
; CHECK-NEXT: [[R:%.*]] = lshr <2 x i32> [[X:%.*]], [[SHAMT_WIDE1]]
; CHECK-NEXT: ret <2 x i32> [[R]]
;
Expand All @@ -57,7 +57,7 @@ define <2 x i32> @t4_vec_lshr(<2 x i32> %x, <2 x i8> %shamt) {
}
define <2 x i32> @t5_vec_ashr(<2 x i32> %x, <2 x i8> %shamt) {
; CHECK-LABEL: @t5_vec_ashr(
; CHECK-NEXT: [[SHAMT_WIDE1:%.*]] = zext <2 x i8> [[SHAMT:%.*]] to <2 x i32>
; CHECK-NEXT: [[SHAMT_WIDE1:%.*]] = zext nneg <2 x i8> [[SHAMT:%.*]] to <2 x i32>
; CHECK-NEXT: [[R:%.*]] = ashr <2 x i32> [[X:%.*]], [[SHAMT_WIDE1]]
; CHECK-NEXT: ret <2 x i32> [[R]]
;
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/Transforms/InstCombine/vector-udiv.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -75,7 +75,7 @@ define <4 x i32> @test_v4i32_shl_const_pow2(<4 x i32> %a0, <4 x i32> %a1) {
define <4 x i32> @test_v4i32_zext_shl_splatconst_pow2(<4 x i32> %a0, <4 x i16> %a1) {
; CHECK-LABEL: @test_v4i32_zext_shl_splatconst_pow2(
; CHECK-NEXT: [[TMP1:%.*]] = add <4 x i16> [[A1:%.*]], <i16 2, i16 2, i16 2, i16 2>
; CHECK-NEXT: [[TMP2:%.*]] = zext <4 x i16> [[TMP1]] to <4 x i32>
; CHECK-NEXT: [[TMP2:%.*]] = zext nneg <4 x i16> [[TMP1]] to <4 x i32>
; CHECK-NEXT: [[TMP3:%.*]] = lshr <4 x i32> [[A0:%.*]], [[TMP2]]
; CHECK-NEXT: ret <4 x i32> [[TMP3]]
;
Expand All @@ -88,7 +88,7 @@ define <4 x i32> @test_v4i32_zext_shl_splatconst_pow2(<4 x i32> %a0, <4 x i16> %
define <4 x i32> @test_v4i32_zext_shl_const_pow2(<4 x i32> %a0, <4 x i16> %a1) {
; CHECK-LABEL: @test_v4i32_zext_shl_const_pow2(
; CHECK-NEXT: [[TMP1:%.*]] = add <4 x i16> [[A1:%.*]], <i16 2, i16 3, i16 4, i16 5>
; CHECK-NEXT: [[TMP2:%.*]] = zext <4 x i16> [[TMP1]] to <4 x i32>
; CHECK-NEXT: [[TMP2:%.*]] = zext nneg <4 x i16> [[TMP1]] to <4 x i32>
; CHECK-NEXT: [[TMP3:%.*]] = lshr <4 x i32> [[A0:%.*]], [[TMP2]]
; CHECK-NEXT: ret <4 x i32> [[TMP3]]
;
Expand Down