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[DAG] Set nneg flag when forming zext in demanded bits #72281

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merged 1 commit into from
Jan 18, 2024

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preames
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@preames preames commented Nov 14, 2023

We do the same for the analogous transform in DAGCombine, but this case was missed in the recent patch which added support for zext nneg.

Sorry for the lack of test coverage. Not sure how to exercise this piece of logic. It appears to have only minimal impact on LIT tests (only test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll), and even then, the changes without it appear uninteresting. Maybe we should remove this transform instead?

We do the same for the analogous transform in DAGCombine, but this case
was missed in the recent patch which added support for zext nneg.

Sorry for the lack of test coverage.  Not sure how to exercise this
piece of logic.  It appears to have only minimal impact on LIT tests
(only test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll),
and even then, the changes without it appear uninteresting.  Maybe
we should remove this transform instead?
@preames preames requested a review from topperc November 14, 2023 16:32
@llvmbot llvmbot added the llvm:SelectionDAG SelectionDAGISel as well label Nov 14, 2023
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llvmbot commented Nov 14, 2023

@llvm/pr-subscribers-llvm-selectiondag

Author: Philip Reames (preames)

Changes

We do the same for the analogous transform in DAGCombine, but this case was missed in the recent patch which added support for zext nneg.

Sorry for the lack of test coverage. Not sure how to exercise this piece of logic. It appears to have only minimal impact on LIT tests (only test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll), and even then, the changes without it appear uninteresting. Maybe we should remove this transform instead?


Full diff: https://github.com/llvm/llvm-project/pull/72281.diff

1 Files Affected:

  • (modified) llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp (+6-2)
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index ed352c86eca06e5..cfdda42c38cf482 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -2468,8 +2468,12 @@ bool TargetLowering::SimplifyDemandedBits(
     if (Known.isNonNegative()) {
       unsigned Opc =
           IsVecInReg ? ISD::ZERO_EXTEND_VECTOR_INREG : ISD::ZERO_EXTEND;
-      if (!TLO.LegalOperations() || isOperationLegal(Opc, VT))
-        return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, Src));
+      if (!TLO.LegalOperations() || isOperationLegal(Opc, VT)) {
+        SDNodeFlags Flags;
+        if (!IsVecInReg)
+          Flags.setNonNeg(true);
+        return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, Src, Flags));
+      }
     }
 
     // Attempt to avoid multi-use ops if we don't need anything from them.

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preames commented Nov 28, 2023

ping

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preames commented Jan 17, 2024

ping, @topperc

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LGTM

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@RKSimon RKSimon left a comment

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LGTM

@preames preames merged commit 0fc5f4b into llvm:main Jan 18, 2024
@preames preames deleted the sdag-zext-nneg-demanded-bits branch January 18, 2024 15:34
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4 participants