Skip to content

Hexagon: Add memw_phys, l2gclean* instructions #72420

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 1 commit into from
Nov 16, 2023
Merged

Hexagon: Add memw_phys, l2gclean* instructions #72420

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
102 changes: 102 additions & 0 deletions llvm/lib/Target/Hexagon/HexagonDepIICScalar.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -117,6 +117,7 @@ def tc_788b1d09 : InstrItinClass;
def tc_78f87ed3 : InstrItinClass;
def tc_7af3a37e : InstrItinClass;
def tc_7b9187d3 : InstrItinClass;
def tc_7c28bd7e : InstrItinClass;
def tc_7c31e19a : InstrItinClass;
def tc_7c6d32e4 : InstrItinClass;
def tc_7d6a2568 : InstrItinClass;
Expand Down Expand Up @@ -212,6 +213,7 @@ def tc_e3d699e3 : InstrItinClass;
def tc_e60def48 : InstrItinClass;
def tc_e9170fb7 : InstrItinClass;
def tc_ed03645c : InstrItinClass;
def tc_ed3f8d2a : InstrItinClass;
def tc_eed07714 : InstrItinClass;
def tc_eeda4109 : InstrItinClass;
def tc_ef921005 : InstrItinClass;
Expand Down Expand Up @@ -869,6 +871,10 @@ class DepScalarItinV55 {
[InstrStage<1, [SLOT0]>], [3, 2],
[Hex_FWD, Hex_FWD]>,

InstrItinData <tc_7c28bd7e, /*tc_st*/
[InstrStage<1, [SLOT0]>], [3],
[Hex_FWD]>,

InstrItinData <tc_7c31e19a, /*tc_st*/
[InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
Expand Down Expand Up @@ -1237,6 +1243,10 @@ class DepScalarItinV55 {
[InstrStage<1, [SLOT2]>], [3, 1],
[Hex_FWD, Hex_FWD]>,

InstrItinData <tc_ed3f8d2a, /*tc_ld*/
[InstrStage<1, [SLOT0]>], [4, 1, 1],
[Hex_FWD, Hex_FWD, Hex_FWD]>,

InstrItinData <tc_eed07714, /*tc_ld*/
[InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
Expand Down Expand Up @@ -1737,6 +1747,10 @@ class DepScalarItinV60 {
[InstrStage<1, [SLOT0]>], [3, 2],
[Hex_FWD, Hex_FWD]>,

InstrItinData <tc_7c28bd7e, /*tc_st*/
[InstrStage<1, [SLOT0]>], [3],
[Hex_FWD]>,

InstrItinData <tc_7c31e19a, /*tc_st*/
[InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
Expand Down Expand Up @@ -2625,6 +2639,10 @@ class DepScalarItinV60se {
InstrStage<1, [CVI_ST]>], [3, 2],
[Hex_FWD, Hex_FWD]>,

InstrItinData <tc_7c28bd7e, /*tc_st*/
[InstrStage<1, [SLOT0]>], [3],
[Hex_FWD]>,

InstrItinData <tc_7c31e19a, /*tc_st*/
[InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
Expand Down Expand Up @@ -3004,6 +3022,10 @@ class DepScalarItinV60se {
InstrStage<1, [CVI_ST]>], [3, 1],
[Hex_FWD, Hex_FWD]>,

InstrItinData <tc_ed3f8d2a, /*tc_ld*/
[InstrStage<1, [SLOT0]>], [4, 1, 1],
[Hex_FWD, Hex_FWD, Hex_FWD]>,

InstrItinData <tc_eed07714, /*tc_ld*/
[InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
Expand Down Expand Up @@ -3509,6 +3531,10 @@ class DepScalarItinV62 {
[InstrStage<1, [SLOT0]>], [3, 2],
[Hex_FWD, Hex_FWD]>,

InstrItinData <tc_7c28bd7e, /*tc_st*/
[InstrStage<1, [SLOT0]>], [3],
[Hex_FWD]>,

InstrItinData <tc_7c31e19a, /*tc_st*/
[InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
Expand Down Expand Up @@ -3877,6 +3903,10 @@ class DepScalarItinV62 {
[InstrStage<1, [SLOT2]>], [3, 1],
[Hex_FWD, Hex_FWD]>,

InstrItinData <tc_ed3f8d2a, /*tc_ld*/
[InstrStage<1, [SLOT0]>], [4, 1, 1],
[Hex_FWD, Hex_FWD, Hex_FWD]>,

InstrItinData <tc_eed07714, /*tc_ld*/
[InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
Expand Down Expand Up @@ -4381,6 +4411,10 @@ class DepScalarItinV65 {
[InstrStage<1, [SLOT0]>], [3, 2],
[Hex_FWD, Hex_FWD]>,

InstrItinData <tc_7c28bd7e, /*tc_st*/
[InstrStage<1, [SLOT0]>], [3],
[Hex_FWD]>,

InstrItinData <tc_7c31e19a, /*tc_st*/
[InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
Expand Down Expand Up @@ -4757,6 +4791,10 @@ class DepScalarItinV65 {
[InstrStage<1, [SLOT2]>], [3, 2],
[Hex_FWD, Hex_FWD]>,

InstrItinData <tc_ed3f8d2a, /*tc_ld*/
[InstrStage<1, [SLOT0]>], [4, 1, 1],
[Hex_FWD, Hex_FWD, Hex_FWD]>,

InstrItinData <tc_eed07714, /*tc_ld*/
[InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
Expand Down Expand Up @@ -5261,6 +5299,10 @@ class DepScalarItinV66 {
[InstrStage<1, [SLOT0]>], [3, 2],
[Hex_FWD, Hex_FWD]>,

InstrItinData <tc_7c28bd7e, /*tc_st*/
[InstrStage<1, [SLOT0]>], [3],
[Hex_FWD]>,

InstrItinData <tc_7c31e19a, /*tc_st*/
[InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
Expand Down Expand Up @@ -5637,6 +5679,10 @@ class DepScalarItinV66 {
[InstrStage<1, [SLOT2]>], [3, 2],
[Hex_FWD, Hex_FWD]>,

InstrItinData <tc_ed3f8d2a, /*tc_ld*/
[InstrStage<1, [SLOT0]>], [4, 1, 1],
[Hex_FWD, Hex_FWD, Hex_FWD]>,

InstrItinData <tc_eed07714, /*tc_ld*/
[InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
Expand Down Expand Up @@ -6141,6 +6187,10 @@ class DepScalarItinV67 {
[InstrStage<1, [SLOT0]>], [3, 2],
[Hex_FWD, Hex_FWD]>,

InstrItinData <tc_7c28bd7e, /*tc_st*/
[InstrStage<1, [SLOT0]>], [3],
[Hex_FWD]>,

InstrItinData <tc_7c31e19a, /*tc_st*/
[InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
Expand Down Expand Up @@ -6521,6 +6571,10 @@ class DepScalarItinV67 {
[InstrStage<1, [SLOT2]>], [3, 2],
[Hex_FWD, Hex_FWD]>,

InstrItinData <tc_ed3f8d2a, /*tc_ld*/
[InstrStage<1, [SLOT0]>], [4, 1, 1],
[Hex_FWD, Hex_FWD, Hex_FWD]>,

InstrItinData <tc_eed07714, /*tc_ld*/
[InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
Expand Down Expand Up @@ -7025,6 +7079,10 @@ class DepScalarItinV67T {
[InstrStage<1, [SLOT0]>], [3, 2],
[Hex_FWD, Hex_FWD]>,

InstrItinData <tc_7c28bd7e, /*tc_st*/
[InstrStage<1, [SLOT0]>], [3],
[Hex_FWD]>,

InstrItinData <tc_7c31e19a, /*tc_st*/
[InstrStage<1, [SLOT0]>], [1, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
Expand Down Expand Up @@ -7401,6 +7459,10 @@ class DepScalarItinV67T {
[InstrStage<1, [SLOT2]>], [3, 2],
[Hex_FWD, Hex_FWD]>,

InstrItinData <tc_ed3f8d2a, /*tc_ld*/
[InstrStage<1, [SLOT0]>], [4, 1, 1],
[Hex_FWD, Hex_FWD, Hex_FWD]>,

InstrItinData <tc_eed07714, /*tc_ld*/
[InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
Expand Down Expand Up @@ -7905,6 +7967,10 @@ class DepScalarItinV68 {
[InstrStage<1, [SLOT0]>], [3, 2],
[Hex_FWD, Hex_FWD]>,

InstrItinData <tc_7c28bd7e, /*tc_st*/
[InstrStage<1, [SLOT0]>], [3],
[Hex_FWD]>,

InstrItinData <tc_7c31e19a, /*tc_st*/
[InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
Expand Down Expand Up @@ -8281,6 +8347,10 @@ class DepScalarItinV68 {
[InstrStage<1, [SLOT2]>], [3, 2],
[Hex_FWD, Hex_FWD]>,

InstrItinData <tc_ed3f8d2a, /*tc_ld*/
[InstrStage<1, [SLOT0]>], [4, 1, 1],
[Hex_FWD, Hex_FWD, Hex_FWD]>,

InstrItinData <tc_eed07714, /*tc_ld*/
[InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
Expand Down Expand Up @@ -8785,6 +8855,10 @@ class DepScalarItinV69 {
[InstrStage<1, [SLOT0]>], [3, 2],
[Hex_FWD, Hex_FWD]>,

InstrItinData <tc_7c28bd7e, /*tc_st*/
[InstrStage<1, [SLOT0]>], [3],
[Hex_FWD]>,

InstrItinData <tc_7c31e19a, /*tc_st*/
[InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
Expand Down Expand Up @@ -9161,6 +9235,10 @@ class DepScalarItinV69 {
[InstrStage<1, [SLOT2]>], [3, 2],
[Hex_FWD, Hex_FWD]>,

InstrItinData <tc_ed3f8d2a, /*tc_ld*/
[InstrStage<1, [SLOT0]>], [4, 1, 1],
[Hex_FWD, Hex_FWD, Hex_FWD]>,

InstrItinData <tc_eed07714, /*tc_ld*/
[InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
Expand Down Expand Up @@ -9665,6 +9743,10 @@ class DepScalarItinV71 {
[InstrStage<1, [SLOT0]>], [3, 2],
[Hex_FWD, Hex_FWD]>,

InstrItinData <tc_7c28bd7e, /*tc_st*/
[InstrStage<1, [SLOT0]>], [3],
[Hex_FWD]>,

InstrItinData <tc_7c31e19a, /*tc_st*/
[InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
Expand Down Expand Up @@ -10041,6 +10123,10 @@ class DepScalarItinV71 {
[InstrStage<1, [SLOT2]>], [3, 2],
[Hex_FWD, Hex_FWD]>,

InstrItinData <tc_ed3f8d2a, /*tc_ld*/
[InstrStage<1, [SLOT0]>], [4, 1, 1],
[Hex_FWD, Hex_FWD, Hex_FWD]>,

InstrItinData <tc_eed07714, /*tc_ld*/
[InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
Expand Down Expand Up @@ -10545,6 +10631,10 @@ class DepScalarItinV71T {
[InstrStage<1, [SLOT0]>], [3, 2],
[Hex_FWD, Hex_FWD]>,

InstrItinData <tc_7c28bd7e, /*tc_st*/
[InstrStage<1, [SLOT0]>], [3],
[Hex_FWD]>,

InstrItinData <tc_7c31e19a, /*tc_st*/
[InstrStage<1, [SLOT0]>], [1, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
Expand Down Expand Up @@ -10921,6 +11011,10 @@ class DepScalarItinV71T {
[InstrStage<1, [SLOT2]>], [3, 2],
[Hex_FWD, Hex_FWD]>,

InstrItinData <tc_ed3f8d2a, /*tc_ld*/
[InstrStage<1, [SLOT0]>], [4, 1, 1],
[Hex_FWD, Hex_FWD, Hex_FWD]>,

InstrItinData <tc_eed07714, /*tc_ld*/
[InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
Expand Down Expand Up @@ -11425,6 +11519,10 @@ class DepScalarItinV73 {
[InstrStage<1, [SLOT0]>], [3, 2],
[Hex_FWD, Hex_FWD]>,

InstrItinData <tc_7c28bd7e, /*tc_st*/
[InstrStage<1, [SLOT0]>], [3],
[Hex_FWD]>,

InstrItinData <tc_7c31e19a, /*tc_st*/
[InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
Expand Down Expand Up @@ -11801,6 +11899,10 @@ class DepScalarItinV73 {
[InstrStage<1, [SLOT2]>], [3, 2],
[Hex_FWD, Hex_FWD]>,

InstrItinData <tc_ed3f8d2a, /*tc_ld*/
[InstrStage<1, [SLOT0]>], [4, 1, 1],
[Hex_FWD, Hex_FWD, Hex_FWD]>,

InstrItinData <tc_eed07714, /*tc_ld*/
[InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2],
[Hex_FWD, Hex_FWD, Hex_FWD]>,
Expand Down
4 changes: 4 additions & 0 deletions llvm/lib/Target/Hexagon/HexagonDepInstrFormats.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1255,6 +1255,10 @@ class Enc_58a8bf : OpcodeHexagon {
bits <5> Rx32;
let Inst{20-16} = Rx32{4-0};
}
class Enc_598f6c : OpcodeHexagon {
bits <5> Rtt32;
let Inst{12-8} = Rtt32{4-0};
}
class Enc_5a18b3 : OpcodeHexagon {
bits <11> Ii;
let Inst{21-20} = Ii{10-9};
Expand Down
34 changes: 34 additions & 0 deletions llvm/lib/Target/Hexagon/HexagonDepInstrInfo.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -12455,6 +12455,20 @@ let isExtentSigned = 0;
let opExtentBits = 6;
let opExtentAlign = 0;
}
def L4_loadw_phys : HInst<
(outs IntRegs:$Rd32),
(ins IntRegs:$Rs32, IntRegs:$Rt32),
"$Rd32 = memw_phys($Rs32,$Rt32)",
tc_ed3f8d2a, TypeLD>, Enc_5ab2be {
let Inst{7-5} = 0b000;
let Inst{13-13} = 0b1;
let Inst{31-21} = 0b10010010000;
let hasNewValue = 1;
let opNewValue = 0;
let accessSize = WordAccess;
let mayLoad = 1;
let isSolo = 1;
}
def L4_or_memopb_io : HInst<
(outs),
(ins IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32),
Expand Down Expand Up @@ -41165,6 +41179,26 @@ let opNewValue = 0;
let hasSideEffects = 1;
let isSolo = 1;
}
def Y6_l2gcleaninvpa : HInst<
(outs),
(ins DoubleRegs:$Rtt32),
"l2gcleaninv($Rtt32)",
tc_7c28bd7e, TypeST>, Enc_598f6c {
let Inst{7-0} = 0b00000000;
let Inst{13-13} = 0b0;
let Inst{31-16} = 0b1010011011000000;
let isSolo = 1;
}
def Y6_l2gcleanpa : HInst<
(outs),
(ins DoubleRegs:$Rtt32),
"l2gclean($Rtt32)",
tc_7c28bd7e, TypeST>, Enc_598f6c {
let Inst{7-0} = 0b00000000;
let Inst{13-13} = 0b0;
let Inst{31-16} = 0b1010011010100000;
let isSolo = 1;
}
def dep_A2_addsat : HInst<
(outs IntRegs:$Rd32),
(ins IntRegs:$Rs32, IntRegs:$Rt32),
Expand Down
Loading