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[SCEVExpander] Attempt to reinfer flags dropped due to CSE #72431

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Merged
merged 3 commits into from
Dec 7, 2023
Merged

[SCEVExpander] Attempt to reinfer flags dropped due to CSE #72431

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93eaadd
[SCEVExpander] Attempt to reinfer flags dropped due to CSE
preames Nov 15, 2023
54f7d6f
Address review comment
preames Dec 7, 2023
70f6434
Test case update after rebase
preames Dec 7, 2023
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20 changes: 19 additions & 1 deletion llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1532,8 +1532,26 @@ Value *SCEVExpander::expand(const SCEV *S) {
V = visit(S);
V = fixupLCSSAFormFor(V);
} else {
for (Instruction *I : DropPoisonGeneratingInsts)
for (Instruction *I : DropPoisonGeneratingInsts) {
I->dropPoisonGeneratingFlagsAndMetadata();
// See if we can re-infer from first principles any of the flags we just
// dropped.
if (auto *OBO = dyn_cast<OverflowingBinaryOperator>(I))
if (auto Flags = SE.getStrengthenedNoWrapFlagsFromBinOp(OBO)) {
auto *BO = cast<BinaryOperator>(I);
BO->setHasNoUnsignedWrap(
ScalarEvolution::maskFlags(*Flags, SCEV::FlagNUW) == SCEV::FlagNUW);
BO->setHasNoSignedWrap(
ScalarEvolution::maskFlags(*Flags, SCEV::FlagNSW) == SCEV::FlagNSW);
}
if (auto *NNI = dyn_cast<PossiblyNonNegInst>(I)) {
auto *Src = NNI->getOperand(0);
if (isImpliedByDomCondition(ICmpInst::ICMP_SGE, Src,
Constant::getNullValue(Src->getType()), I,
DL).value_or(false))
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@nikic nikic Nov 28, 2023 •
edited
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It looks like you don't have test coverage for all three of these calls. (Edit: As in, only one out of three is covered.)

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Generally I'd expect ValueTracking isKnownNonNegative to not give any useful additional information here, with the exception of assume s.

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Deleted for now. I'd originally intended for this to be read along side #72437, but let's keep them separate for now.

NNI->setNonNeg(true);
}
}
}
// Remember the expanded value for this SCEV at this location.
//
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3 changes: 1 addition & 2 deletions llvm/test/CodeGen/RISCV/riscv-codegenprepare-asm.ll
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Expand Up @@ -10,8 +10,7 @@ define void @test1(ptr nocapture noundef %a, i32 noundef signext %n) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: blez a1, .LBB0_3
; CHECK-NEXT: # %bb.1: # %for.body.preheader
; CHECK-NEXT: slli a1, a1, 32
; CHECK-NEXT: srli a1, a1, 30
; CHECK-NEXT: slli a1, a1, 2
; CHECK-NEXT: add a1, a0, a1
; CHECK-NEXT: .LBB0_2: # %for.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
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12 changes: 5 additions & 7 deletions llvm/test/CodeGen/Thumb2/mve-blockplacement.ll
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Expand Up @@ -385,19 +385,17 @@ define i32 @d(i64 %e, i32 %f, i64 %g, i32 %h) {
; CHECK-NEXT: @ implicit-def: $r11
; CHECK-NEXT: mov.w r9, #12
; CHECK-NEXT: str r4, [sp, #12] @ 4-byte Spill
; CHECK-NEXT: add.w r0, r0, r2, lsr #1
; CHECK-NEXT: add.w r1, r1, r2, lsr #1
; CHECK-NEXT: movw r2, #65532
; CHECK-NEXT: vdup.32 q6, r0
; CHECK-NEXT: movt r2, #32767
; CHECK-NEXT: and.w r3, r1, r2
; CHECK-NEXT: add.w r0, r0, r2, lsr #1
; CHECK-NEXT: bic r3, r1, #3
; CHECK-NEXT: adr r1, .LCPI1_0
; CHECK-NEXT: vdup.32 q7, r0
; CHECK-NEXT: vldrw.u32 q0, [r1]
; CHECK-NEXT: adr r1, .LCPI1_1
; CHECK-NEXT: vldrw.u32 q5, [r1]
; CHECK-NEXT: strd r3, r7, [sp, #4] @ 8-byte Folded Spill
; CHECK-NEXT: vdup.32 q6, r0
; CHECK-NEXT: vadd.i32 q4, q0, r7
; CHECK-NEXT: vdup.32 q7, r0
; CHECK-NEXT: strd r3, r7, [sp, #4] @ 8-byte Folded Spill
; CHECK-NEXT: b .LBB1_6
; CHECK-NEXT: .LBB1_2: @ %for.body6.preheader
; CHECK-NEXT: @ in Loop: Header=BB1_6 Depth=1
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2 changes: 1 addition & 1 deletion llvm/test/Transforms/IRCE/non-loop-invariant-rhs-instr.ll
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Expand Up @@ -9,7 +9,7 @@ define i32 @test_01(i32 %A, i64 %Len, ptr %array) {
; CHECK-NEXT: br i1 [[TRIPCHECK]], label [[LOOP_PREHEADER:%.*]], label [[ZERO:%.*]]
; CHECK: loop.preheader:
; CHECK-NEXT: [[TMP0:%.*]] = zext i32 [[A:%.*]] to i64
; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[TMP0]], 1
; CHECK-NEXT: [[TMP1:%.*]] = add nuw nsw i64 [[TMP0]], 1
; CHECK-NEXT: [[SMIN:%.*]] = call i64 @llvm.smin.i64(i64 [[LEN]], i64 0)
; CHECK-NEXT: [[TMP2:%.*]] = sub i64 [[LEN]], [[SMIN]]
; CHECK-NEXT: [[UMIN:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP2]], i64 [[TMP1]])
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2 changes: 1 addition & 1 deletion llvm/test/Transforms/IndVarSimplify/promote-iv-to-eliminate-casts.ll
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Expand Up @@ -182,7 +182,7 @@ define void @promote_latch_condition_decrementing_loop_01(ptr %p, ptr %a) {
; CHECK-LABEL: @promote_latch_condition_decrementing_loop_01(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[LEN:%.*]] = load i32, ptr [[P:%.*]], align 4, !range [[RNG0:![0-9]+]]
; CHECK-NEXT: [[LEN_MINUS_1:%.*]] = add i32 [[LEN]], -1
; CHECK-NEXT: [[LEN_MINUS_1:%.*]] = add nsw i32 [[LEN]], -1
; CHECK-NEXT: [[ZERO_CHECK:%.*]] = icmp eq i32 [[LEN]], 0
; CHECK-NEXT: br i1 [[ZERO_CHECK]], label [[LOOPEXIT:%.*]], label [[PREHEADER:%.*]]
; CHECK: preheader:
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2 changes: 1 addition & 1 deletion llvm/test/Transforms/LoopPredication/basic.ll
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Expand Up @@ -1681,7 +1681,7 @@ define i32 @ne_latch_zext(ptr %array, i32 %length, i16 %n16) {
; CHECK-LABEL: @ne_latch_zext(
; CHECK-NEXT: loop.preheader:
; CHECK-NEXT: [[N:%.*]] = zext i16 [[N16:%.*]] to i32
; CHECK-NEXT: [[NPLUS1:%.*]] = add i32 [[N]], 1
; CHECK-NEXT: [[NPLUS1:%.*]] = add nuw nsw i32 [[N]], 1
; CHECK-NEXT: [[TMP0:%.*]] = icmp ule i32 [[NPLUS1]], [[LENGTH:%.*]]
; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i32 0, [[LENGTH]]
; CHECK-NEXT: [[TMP2:%.*]] = and i1 [[TMP1]], [[TMP0]]
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2 changes: 1 addition & 1 deletion llvm/test/Transforms/LoopUnroll/runtime-exit-phi-scev-invalidation.ll
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Expand Up @@ -96,7 +96,7 @@ define void @pr56282() {
; CHECK: inner.2.preheader:
; CHECK-NEXT: br label [[INNER_2]]
; CHECK: inner.2:
; CHECK-NEXT: [[OUTER_IV_NEXT]] = add i64 [[OUTER_IV]], 1
; CHECK-NEXT: [[OUTER_IV_NEXT]] = add nuw i64 [[OUTER_IV]], 1
; CHECK-NEXT: br label [[OUTER_HEADER]]
; CHECK: exit:
; CHECK-NEXT: ret void
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