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[AMDGPU] Allocate i1 argument to SGPRs #72461

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75f1a46
[AMDGPU] Allocate i1 argument to SGPRs
Nov 16, 2023
67365b8
Fix format.
Nov 16, 2023
ae46c82
Creating a custom calling conv function for i1.
Nov 30, 2023
721c34d
Fix formatting.
Dec 1, 2023
ca09ddd
Fixed (1) problems for global-isel wrt both incoming args and return
Dec 21, 2023
f26afca
Minor changes based on code review.
Jan 16, 2024
26fa9cc
Additional change based on code review.
Jan 22, 2024
3b323d9
Changing a vector of 4 registers to a single register.
Jan 31, 2024
b4c0bb9
Update some test files.
Feb 2, 2024
ad7d657
Updated calling conv such that inreg i1 is promoted to i32 before
Feb 20, 2024
d841a49
Add an additional CopyToReg and CopyFromReg for the CopyFromReg
Mar 11, 2024
df1bbe3
Revert a formatting change made by clang-format.
Mar 11, 2024
4c098fe
This commit: (1) fixed i1 array as func return (2) fixed i1 return when
Mar 21, 2024
e6e574d
This commit: (1) a fix for i1 return with GlobalISel (2) testcases.
Mar 22, 2024
4f54c98
Fix formatting.
Mar 22, 2024
a79ddae
Use update_llc_test_checks.py on new test files; remove incorrect
Apr 1, 2024
d3338c9
For GlobalISel: (1) for incoming i1 arg/return, do not generate G_TRUNC;
Apr 30, 2024
4a82212
(1) avoid using reserved ScratchRSrcReg (2) update/add testcases.
May 13, 2024
c0dfff7
Testcase updates.
May 13, 2024
6f2289b
Fix test file after merge from main.
May 13, 2024
265d5c6
(1) Fix a problem with reserving ScratchRSrcD (2) update test files.
May 14, 2024
6aaa564
Overload the function CallLowering::determineAndHandleAssignments() with
May 28, 2024
4892dc7
For i1 arg, set reg bank in RegBankSelect, instead of setting reg class
May 28, 2024
da176a8
For i1 function return value, an additional CopyFromReg is created to
Jun 5, 2024
df3a52e
Undo 6aaa564, i.e., remove the overloaded
Jun 6, 2024
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55 changes: 50 additions & 5 deletions llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -63,6 +63,12 @@ struct AMDGPUOutgoingValueHandler : public CallLowering::OutgoingValueHandler {

void assignValueToReg(Register ValVReg, Register PhysReg,
const CCValAssign &VA) override {
if (VA.getLocVT() == MVT::i1) {
MIRBuilder.buildCopy(PhysReg, ValVReg);
MIB.addUse(PhysReg, RegState::Implicit);
return;
}

Register ExtReg = extendRegisterMin32(*this, ValVReg, VA);

// If this is a scalar return, insert a readfirstlane just in case the value
Expand Down Expand Up @@ -121,6 +127,11 @@ struct AMDGPUIncomingArgHandler : public CallLowering::IncomingValueHandler {
const CCValAssign &VA) override {
markPhysRegUsed(PhysReg);

if (VA.getLocVT() == MVT::i1) {
MIRBuilder.buildCopy(ValVReg, PhysReg);
return;
}

if (VA.getLocVT().getSizeInBits() < 32) {
// 16-bit types are reported as legal for 32-bit registers. We need to do
// a 32-bit copy, and truncate to avoid the verifier complaining about it.
Expand Down Expand Up @@ -233,6 +244,12 @@ struct AMDGPUOutgoingArgHandler : public AMDGPUOutgoingValueHandler {
void assignValueToReg(Register ValVReg, Register PhysReg,
const CCValAssign &VA) override {
MIB.addUse(PhysReg, RegState::Implicit);

if (VA.getLocVT() == MVT::i1) {
MIRBuilder.buildCopy(PhysReg, ValVReg);
return;
}

Register ExtReg = extendRegisterMin32(*this, ValVReg, VA);
MIRBuilder.buildCopy(PhysReg, ExtReg);
}
Expand Down Expand Up @@ -260,7 +277,7 @@ struct AMDGPUOutgoingArgHandler : public AMDGPUOutgoingValueHandler {
assignValueToAddress(ValVReg, Addr, MemTy, MPO, VA);
}
};
}
} // namespace

AMDGPUCallLowering::AMDGPUCallLowering(const AMDGPUTargetLowering &TLI)
: CallLowering(&TLI) {
Expand Down Expand Up @@ -358,8 +375,19 @@ bool AMDGPUCallLowering::lowerReturnVal(MachineIRBuilder &B,

OutgoingValueAssigner Assigner(AssignFn);
AMDGPUOutgoingValueHandler RetHandler(B, *MRI, Ret);
return determineAndHandleAssignments(RetHandler, Assigner, SplitRetInfos, B,
CC, F.isVarArg());

SmallVector<CCValAssign, 16> ArgLocs;
CCState CCInfo(CC, F.isVarArg(), MF, ArgLocs, F.getContext());

const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
if (!ST.enableFlatScratch()) {
SIMachineFunctionInfo *FuncInfo = MF.getInfo<SIMachineFunctionInfo>();
CCInfo.AllocateReg(FuncInfo->getScratchRSrcReg());
}
if (!determineAssignments(Assigner, SplitRetInfos, CCInfo))
return false;

return handleAssignments(RetHandler, SplitRetInfos, CCInfo, ArgLocs, B);
}

bool AMDGPUCallLowering::lowerReturn(MachineIRBuilder &B, const Value *Val,
Expand Down Expand Up @@ -1473,6 +1501,11 @@ bool AMDGPUCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
return false;
}

if (!ST.enableFlatScratch()) {
SIMachineFunctionInfo *FuncInfo = MF.getInfo<SIMachineFunctionInfo>();
CCInfo.AllocateReg(FuncInfo->getScratchRSrcReg());
}

// Do the actual argument marshalling.
SmallVector<Register, 8> PhysRegs;

Expand Down Expand Up @@ -1519,8 +1552,20 @@ bool AMDGPUCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
Info.IsVarArg);
IncomingValueAssigner Assigner(RetAssignFn);
CallReturnHandler Handler(MIRBuilder, MRI, MIB);
if (!determineAndHandleAssignments(Handler, Assigner, InArgs, MIRBuilder,
Info.CallConv, Info.IsVarArg))

SmallVector<CCValAssign, 16> ArgLocs;
CCState CCInfo(Info.CallConv, Info.IsVarArg, MF, ArgLocs, F.getContext());

const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
if (!ST.enableFlatScratch()) {
SIMachineFunctionInfo *FuncInfo = MF.getInfo<SIMachineFunctionInfo>();
CCInfo.AllocateReg(FuncInfo->getScratchRSrcReg());
}

if (!determineAssignments(Assigner, InArgs, CCInfo))
return false;

if (!handleAssignments(Handler, InArgs, CCInfo, ArgLocs, MIRBuilder))
return false;
}

Expand Down
13 changes: 10 additions & 3 deletions llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td
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Original file line number Diff line number Diff line change
Expand Up @@ -187,13 +187,17 @@ def CSR_AMDGPU_NoRegs : CalleeSavedRegs<(add)>;
// Calling convention for leaf functions
def CC_AMDGPU_Func : CallingConv<[
CCIfByVal<CCPassByVal<4, 4>>,
CCIfType<[i1], CCPromoteToType<i32>>,
CCIfType<[i1], CCIfInReg<CCPromoteToType<i32>>>,
CCIfType<[i8, i16], CCIfExtend<CCPromoteToType<i32>>>,

CCIfInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16, bf16, v2bf16] , CCAssignToReg<
!foreach(i, !range(0, 30), !cast<Register>("SGPR"#i)) // SGPR0-29
>>>,

CCIfType<[i1], CCCustom<"CC_AMDGPU_Custom_I1">>,

CCIfType<[i1], CCPromoteToType<i32>>,

CCIfType<[i32, f32, i16, f16, v2i16, v2f16, i1, bf16, v2bf16], CCAssignToReg<[
VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7,
VGPR8, VGPR9, VGPR10, VGPR11, VGPR12, VGPR13, VGPR14, VGPR15,
Expand All @@ -204,8 +208,11 @@ def CC_AMDGPU_Func : CallingConv<[

// Calling convention for leaf functions
def RetCC_AMDGPU_Func : CallingConv<[
CCIfType<[i1], CCPromoteToType<i32>>,
CCIfType<[i1, i16], CCIfExtend<CCPromoteToType<i32>>>,
CCIfType<[i16], CCIfExtend<CCPromoteToType<i32>>>,
CCIfType<[i1], CCIfInReg<CCPromoteToType<i32>>>,

CCIfType<[i1] , CCCustom<"CC_AMDGPU_Custom_I1">>,

CCIfType<[i32, f32, i16, f16, v2i16, v2f16, bf16, v2bf16], CCAssignToReg<[
VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7,
VGPR8, VGPR9, VGPR10, VGPR11, VGPR12, VGPR13, VGPR14, VGPR15,
Expand Down
35 changes: 35 additions & 0 deletions llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -29,6 +29,38 @@

using namespace llvm;

static bool CC_AMDGPU_Custom_I1(unsigned ValNo, MVT ValVT, MVT LocVT,
CCValAssign::LocInfo LocInfo,
ISD::ArgFlagsTy ArgFlags, CCState &State) {
static bool IsWave64 =
State.getMachineFunction().getSubtarget<GCNSubtarget>().isWave64();

static const MCPhysReg SGPRArgsWave64[] = {
AMDGPU::SGPR0_SGPR1, AMDGPU::SGPR2_SGPR3, AMDGPU::SGPR4_SGPR5,
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Do we want to only pass in even aligned registers? We could also include all the aliasing odd-based cases

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By "odd-based cases" do you mean something like SGPR1_SGPR2? Do you have an example where such reg allocation is used?

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Yes. I mean if you had (i32 inreg %arg0, i64 inreg %arg1), you could use arg0=s0, arg1=s[1:2]

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This issue deals with i1 arg/return only. Inreg args are handled separately. If you are thinking about a mixed case as follows:

foo (i32 inreg %arg0, i1 %arg1)

Currently for gfx900, %arg0 is assigned to s4, and %arg1 to s[6:7]. If in this case you want %arg1 to be given s[5:6], I suppose the list of registers can be changed from { ... sgpr4_sgpr5, sgpr6_sgpr7, ...} to {... sgpr4_sgpr5, sgpr5_sgrp6, sgpr6_sgrp7, ...}.
Is this what you had in mind?

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@arsenm Pls let me know if the above is what you wanted.

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Yes, the i64 is physically what is being passed, but doesn't have the alignment requirement in the argument list.

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It seems pairs of SGPRs that start with an odd number, e.g., SGPR5_SGPR6, are
not defined. Only pairs like SGPR4_SGPR5 are defined.

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Yes, you have to unroll them into the 32-bit pieces and reassemble the virtual register

AMDGPU::SGPR6_SGPR7, AMDGPU::SGPR8_SGPR9, AMDGPU::SGPR10_SGPR11,
AMDGPU::SGPR12_SGPR13, AMDGPU::SGPR14_SGPR15, AMDGPU::SGPR16_SGPR17,
AMDGPU::SGPR18_SGPR19, AMDGPU::SGPR20_SGPR21, AMDGPU::SGPR22_SGPR23,
AMDGPU::SGPR24_SGPR25, AMDGPU::SGPR26_SGPR27, AMDGPU::SGPR28_SGPR29};

static const MCPhysReg SGPRArgsWave32[] = {
AMDGPU::SGPR0, AMDGPU::SGPR1, AMDGPU::SGPR2, AMDGPU::SGPR3,
AMDGPU::SGPR4, AMDGPU::SGPR5, AMDGPU::SGPR6, AMDGPU::SGPR7,
AMDGPU::SGPR8, AMDGPU::SGPR9, AMDGPU::SGPR10, AMDGPU::SGPR11,
AMDGPU::SGPR12, AMDGPU::SGPR13, AMDGPU::SGPR14, AMDGPU::SGPR15,
AMDGPU::SGPR16, AMDGPU::SGPR17, AMDGPU::SGPR18, AMDGPU::SGPR19,
AMDGPU::SGPR20, AMDGPU::SGPR21, AMDGPU::SGPR22, AMDGPU::SGPR23,
AMDGPU::SGPR24, AMDGPU::SGPR25, AMDGPU::SGPR26, AMDGPU::SGPR27,
AMDGPU::SGPR28, AMDGPU::SGPR29};

assert(LocVT == MVT::i1);
if (unsigned Reg = IsWave64 ? State.AllocateReg(SGPRArgsWave64)
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Could you avoid the determineAndHandleAssignments changes by using drop_front if !enableFlatScratch?

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If we use drop_front, doesn't that mean we are assuming that the reserved reg is s[0:3]? How about putting in here something like the following:

     if (!Subtarget.enableFlatScratch())
       CCInfo.AllocateReg(Info->getScratchRSrcReg());

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Yes, could also do that

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Decided to create an overload function determineAndHandleAssignments() instead.

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See above, might as well just use the 2 pieces of determineAndHandleAssignments instead

: State.AllocateReg(SGPRArgsWave32)) {
State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
return true;
}
return false; // not allocated
}

#include "AMDGPUGenCallingConv.inc"

static cl::opt<bool> AMDGPUBypassSlowDiv(
Expand Down Expand Up @@ -784,6 +816,9 @@ EVT AMDGPUTargetLowering::getTypeForExtReturn(LLVMContext &Context, EVT VT,
ISD::NodeType ExtendKind) const {
assert(!VT.isVector() && "only scalar expected");

if (VT == MVT::i1)
return MVT::i1;

// Round to the next multiple of 32-bits.
unsigned Size = VT.getSizeInBits();
if (Size <= 32)
Expand Down
6 changes: 6 additions & 0 deletions llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
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Expand Up @@ -131,6 +131,12 @@ bool AMDGPUInstructionSelector::selectCOPY(MachineInstr &I) const {
Register SrcReg = Src.getReg();

if (isVCC(DstReg, *MRI)) {
if (SrcReg.isPhysical() && SrcReg != AMDGPU::SCC) {
const TargetRegisterClass *DstRC = MRI->getRegClassOrNull(DstReg);
if (DstRC)
return DstRC->contains(SrcReg);
}
Comment on lines +134 to +138
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Can you split this into a separate change, with MIR tests? I suspect you can just directly return true.

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This should be split to a separate change


if (SrcReg == AMDGPU::SCC) {
const TargetRegisterClass *RC
= TRI.getConstrainedRegClassForOperand(Dst, *MRI);
Expand Down
13 changes: 13 additions & 0 deletions llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
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Expand Up @@ -3741,6 +3741,19 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
if (!DstBank)
DstBank = SrcBank;

// For i1 function arguments, the call of getRegBank() currently gives
// incorrect result. We set both src and dst banks to VCCRegBank.
if (!MI.getOperand(1).getReg().isVirtual() &&
MRI.getType(MI.getOperand(0).getReg()) == LLT::scalar(1)) {
DstBank = SrcBank = &AMDGPU::VCCRegBank;
}

// For i1 return value, the dst reg is an SReg but we need to set the reg
// bank to VCCRegBank.
if (!MI.getOperand(0).getReg().isVirtual() &&
SrcBank == &AMDGPU::VCCRegBank)
DstBank = SrcBank;

Comment on lines +3744 to +3756
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Can you also make this a separate PR (I want 2, one for the RegBankSelect and one for the InstructionSelect parts)

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Ping

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Are you saying that the changes in AMDGPURegisterBankInfo.cpp should be a separate PR? Without those changes, I think some testcases will fail.

unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI);
if (MI.getOpcode() != AMDGPU::G_FREEZE &&
cannotCopy(*DstBank, *SrcBank, TypeSize::getFixed(Size)))
Expand Down
47 changes: 45 additions & 2 deletions llvm/lib/Target/AMDGPU/SIISelLowering.cpp
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Expand Up @@ -3026,8 +3026,13 @@ SDValue SITargetLowering::LowerFormalArguments(
RC = &AMDGPU::VGPR_32RegClass;
else if (AMDGPU::SGPR_32RegClass.contains(Reg))
RC = &AMDGPU::SGPR_32RegClass;
else
llvm_unreachable("Unexpected register class in LowerFormalArguments!");
else {
if (VT == MVT::i1)
RC = Subtarget->getBoolRC();
else
llvm_unreachable("Unexpected register class in LowerFormalArguments!");
}

EVT ValVT = VA.getValVT();

Reg = MF.addLiveIn(Reg, RC);
Expand Down Expand Up @@ -3144,6 +3149,9 @@ SITargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
*DAG.getContext());

if (!Subtarget->enableFlatScratch())
CCInfo.AllocateReg(Info->getScratchRSrcReg());

// Analyze outgoing return values.
CCInfo.AnalyzeReturn(Outs, CCAssignFnForReturn(CallConv, isVarArg));

Expand Down Expand Up @@ -3223,6 +3231,13 @@ SDValue SITargetLowering::LowerCallResult(
SmallVector<CCValAssign, 16> RVLocs;
CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
*DAG.getContext());

if (!Subtarget->enableFlatScratch()) {
SIMachineFunctionInfo *FuncInfo =
DAG.getMachineFunction().getInfo<SIMachineFunctionInfo>();
CCInfo.AllocateReg(FuncInfo->getScratchRSrcReg());
}

CCInfo.AnalyzeCallResult(Ins, RetCC);

// Copy all of the result registers out of their specified physreg.
Expand All @@ -3234,6 +3249,23 @@ SDValue SITargetLowering::LowerCallResult(
Val = DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), VA.getLocVT(), InGlue);
Chain = Val.getValue(1);
InGlue = Val.getValue(2);

// For i1 return value allocated to an SGPR, the following is a
// workaround before SILowerI1Copies is fixed. Basically we want the
// dst reg for the above CopyFromReg not to be of the VReg_1 class
// when emitting machine code. This workaround creats an addional
// CopyToReg with a new virtual register, followed by another
// CopyFromReg.
if (VA.getLocVT() == MVT::i1) {
const SIRegisterInfo *TRI = Subtarget->getRegisterInfo();
MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();

if (TRI->isSGPRReg(MRI, VA.getLocReg())) {
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This should always be true if LocVT is i1

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So far only CC_AMDGPU_Func/RetCC_AMDGPU_Func have been modified such that i1 arg/return are put in SGPRs. Therefore, other calling conv functions still use VGPRs. Do you want all the others to be changed as well?

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@arsenm arsenm May 9, 2024 •
edited
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amdgpu_gfx should be the same. The others are entry points where we can't just change this

Register TmpVReg = MRI.createVirtualRegister(TRI->getBoolRC());
SDValue TmpCopyTo = DAG.getCopyToReg(Chain, DL, TmpVReg, Val);
Val = DAG.getCopyFromReg(TmpCopyTo, DL, VA.getLocReg(), MVT::i1);
}
}
} else if (VA.isMemLoc()) {
report_fatal_error("TODO: return values in memory");
} else
Expand Down Expand Up @@ -3668,6 +3700,17 @@ SDValue SITargetLowering::LowerCall(CallLoweringInfo &CLI,
passSpecialInputs(CLI, CCInfo, *Info, RegsToPass, MemOpChains, Chain);
}

// In code below (after call of AnalyzeCallOperands),
// if (!Subtarget->enableFlatScratch()), it would use either s[48:51] or
// s[0:3]. Therefore, before calling AnalyzeCallOperands, we may need to
// reserve these registers.
if (!Subtarget->enableFlatScratch()) {
if (IsChainCallConv)
CCInfo.AllocateReg(AMDGPU::SGPR48_SGPR49_SGPR50_SGPR51);
else
CCInfo.AllocateReg(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3);
}

Comment on lines +3703 to +3713
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Unrelated change?

CCInfo.AnalyzeCallOperands(Outs, AssignFn);

// Get a count of how many bytes are to be pushed on the stack.
Expand Down
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