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[InstCombine] Preserve NSW flags for lshr (mul nuw X, C1), C2 -> mul nuw nsw X, (C1 >> C2) #72625

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Merged
merged 1 commit into from
Nov 17, 2023
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[InstCombine] Preserve NSW flags for lshr (mul nuw X, C1), C2 -> mul nuw nsw X, (C1 >> C2) #72625

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7 changes: 4 additions & 3 deletions llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1435,12 +1435,13 @@ Instruction *InstCombinerImpl::visitLShr(BinaryOperator &I) {
if (Op0->hasOneUse()) {
APInt NewMulC = MulC->lshr(ShAmtC);
// if c is divisible by (1 << ShAmtC):
// lshr (mul nuw x, MulC), ShAmtC -> mul nuw x, (MulC >> ShAmtC)
// lshr (mul nuw x, MulC), ShAmtC -> mul nuw nsw x, (MulC >> ShAmtC)
if (MulC->eq(NewMulC.shl(ShAmtC))) {
auto *NewMul =
BinaryOperator::CreateNUWMul(X, ConstantInt::get(Ty, NewMulC));
BinaryOperator *OrigMul = cast<BinaryOperator>(Op0);
NewMul->setHasNoSignedWrap(OrigMul->hasNoSignedWrap());
assert(ShAmtC != 0 &&
"lshr X, 0 should be handled by simplifyLShrInst.");
NewMul->setHasNoSignedWrap(true);
return NewMul;
}
}
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4 changes: 2 additions & 2 deletions llvm/test/Transforms/InstCombine/shift-logic.ll
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Expand Up @@ -259,7 +259,7 @@ define i32 @PR44028(i32 %x) {

define i64 @lshr_mul(i64 %0) {
; CHECK-LABEL: @lshr_mul(
; CHECK-NEXT: [[TMP2:%.*]] = mul nuw i64 [[TMP0:%.*]], 13
; CHECK-NEXT: [[TMP2:%.*]] = mul nuw nsw i64 [[TMP0:%.*]], 13
; CHECK-NEXT: ret i64 [[TMP2]]
;
%2 = mul nuw i64 %0, 52
Expand All @@ -279,7 +279,7 @@ define i64 @lshr_mul_nuw_nsw(i64 %0) {

define <4 x i32> @lshr_mul_vector(<4 x i32> %0) {
; CHECK-LABEL: @lshr_mul_vector(
; CHECK-NEXT: [[TMP2:%.*]] = mul nuw <4 x i32> [[TMP0:%.*]], <i32 13, i32 13, i32 13, i32 13>
; CHECK-NEXT: [[TMP2:%.*]] = mul nuw nsw <4 x i32> [[TMP0:%.*]], <i32 13, i32 13, i32 13, i32 13>
; CHECK-NEXT: ret <4 x i32> [[TMP2]]
;
%2 = mul nuw <4 x i32> %0, <i32 52, i32 52, i32 52, i32 52>
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