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[RISCV] Add register bank and instruction selection support for FP G_SELECT. #72726

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Merged
merged 6 commits into from
Nov 27, 2023
Merged

[RISCV] Add register bank and instruction selection support for FP G_SELECT. #72726

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0792f67
[RISCV] Add register bank and instruction selection support for G_SEL…
topperc Nov 17, 2023
4704a36
fixup! clang-format
topperc Nov 18, 2023
3b69d37
Add f32 test for rv64.
topperc Nov 18, 2023
3353375
fixup! Update comment copy/pasted from AArch64.
topperc Nov 27, 2023
0d20ddf
fixup! Add s32 regbank test for rv64.
topperc Nov 27, 2023
fa54dde
fixup! add more tests.
topperc Nov 27, 2023
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13 changes: 11 additions & 2 deletions llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -912,8 +912,17 @@ bool RISCVInstructionSelector::selectSelect(MachineInstr &MI,
RISCVCC::CondCode CC;
getOperandsForBranch(SelectMI.getCondReg(), MRI, CC, LHS, RHS);

MachineInstr *Result = MIB.buildInstr(RISCV::Select_GPR_Using_CC_GPR)
.addDef(SelectMI.getReg(0))
Register DstReg = SelectMI.getReg(0);

unsigned Opc = RISCV::Select_GPR_Using_CC_GPR;
if (RBI.getRegBank(DstReg, MRI, TRI)->getID() == RISCV::FPRBRegBankID) {
unsigned Size = MRI.getType(DstReg).getSizeInBits();
Opc = Size == 32 ? RISCV::Select_FPR32_Using_CC_GPR
: RISCV::Select_FPR64_Using_CC_GPR;
}

MachineInstr *Result = MIB.buildInstr(Opc)
.addDef(DstReg)
.addReg(LHS)
.addReg(RHS)
.addImm(CC)
Expand Down
53 changes: 49 additions & 4 deletions llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -323,12 +323,57 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
OpdsMapping[0] = getFPValueMapping(Ty.getSizeInBits());
break;
}
case TargetOpcode::G_SELECT:
OpdsMapping[0] = GPRValueMapping;
case TargetOpcode::G_SELECT: {
LLT Ty = MRI.getType(MI.getOperand(0).getReg());

// Try to minimize the number of copies. If we have more floating point
// constrained values than not, then we'll put everything on FPR. Otherwise,
// everything has to be on GPR.
unsigned NumFP = 0;

// Check if the uses of the result always produce floating point values.
//
// For example:
//
// %z = G_SELECT %cond %x %y
// fpr = G_FOO %z ...
if (any_of(MRI.use_nodbg_instructions(MI.getOperand(0).getReg()),
[&](const MachineInstr &UseMI) {
return onlyUsesFP(UseMI, MRI, TRI);
}))
++NumFP;

// Check if the defs of the source values always produce floating point
// values.
//
// For example:
//
// %x = G_SOMETHING_ALWAYS_FLOAT %a ...
// %z = G_SELECT %cond %x %y
//
// Also check whether or not the sources have already been decided to be
// FPR. Keep track of this.
//
// This doesn't check the condition, since the condition is always an
// integer.
for (unsigned Idx = 2; Idx < 4; ++Idx) {
Register VReg = MI.getOperand(Idx).getReg();
MachineInstr *DefMI = MRI.getVRegDef(VReg);
if (getRegBank(VReg, MRI, TRI) == &RISCV::FPRBRegBank ||
onlyDefinesFP(*DefMI, MRI, TRI))
++NumFP;
}

// Condition operand is always GPR.
OpdsMapping[1] = GPRValueMapping;
OpdsMapping[2] = GPRValueMapping;
OpdsMapping[3] = GPRValueMapping;

const ValueMapping *Mapping = GPRValueMapping;
if (NumFP >= 2)
Mapping = getFPValueMapping(Ty.getSizeInBits());

OpdsMapping[0] = OpdsMapping[2] = OpdsMapping[3] = Mapping;
break;
}
case TargetOpcode::G_FPTOSI:
case TargetOpcode::G_FPTOUI:
case RISCV::G_FCLASS: {
Expand Down
33 changes: 33 additions & 0 deletions llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-select-rv32.mir
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@@ -0,0 +1,33 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=instruction-select \
# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s

---
name: fp_select_s32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $x10, $f10_f, $f11_f

; CHECK-LABEL: name: fp_select_s32
; CHECK: liveins: $x10, $f10_f, $f11_f
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f10_f
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr32 = COPY $f11_f
; CHECK-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY]], 1
; CHECK-NEXT: [[Select_FPR32_Using_CC_GPR:%[0-9]+]]:fpr32 = Select_FPR32_Using_CC_GPR [[ANDI]], $x0, 1, [[COPY1]], [[COPY2]]
; CHECK-NEXT: $f10_f = COPY [[Select_FPR32_Using_CC_GPR]]
; CHECK-NEXT: PseudoRET implicit $f10_f
%0:gprb(s32) = COPY $x10
%1:fprb(s32) = COPY $f10_f
%2:fprb(s32) = COPY $f11_f
%3:gprb(s32) = G_CONSTANT i32 1
%4:gprb(s32) = G_AND %0, %3
%5:fprb(s32) = G_SELECT %4(s32), %1, %2
$f10_f = COPY %5(s32)
PseudoRET implicit $f10_f

...
64 changes: 64 additions & 0 deletions llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-select-rv64.mir
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@@ -0,0 +1,64 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=instruction-select \
# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s

---
name: fp_select_s32
alignment: 1
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $x10, $f10_d, $f11_d

; CHECK-LABEL: name: fp_select_s32
; CHECK: liveins: $x10, $f10_d, $f11_d
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f10_f
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr32 = COPY $f11_f
; CHECK-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY]], 1
; CHECK-NEXT: [[Select_FPR32_Using_CC_GPR:%[0-9]+]]:fpr32 = Select_FPR32_Using_CC_GPR [[ANDI]], $x0, 1, [[COPY1]], [[COPY2]]
; CHECK-NEXT: $f10_f = COPY [[Select_FPR32_Using_CC_GPR]]
; CHECK-NEXT: PseudoRET implicit $f10_f
%0:gprb(s64) = COPY $x10
%1:fprb(s32) = COPY $f10_f
%2:fprb(s32) = COPY $f11_f
%3:gprb(s64) = G_CONSTANT i64 1
%4:gprb(s64) = G_AND %0, %3
%5:fprb(s32) = G_SELECT %4(s64), %1, %2
$f10_f = COPY %5(s32)
PseudoRET implicit $f10_f

...
---
name: fp_select_s64
alignment: 1
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $x10, $f10_d, $f11_d

; CHECK-LABEL: name: fp_select_s64
; CHECK: liveins: $x10, $f10_d, $f11_d
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f10_d
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY $f11_d
; CHECK-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY]], 1
; CHECK-NEXT: [[Select_FPR64_Using_CC_GPR:%[0-9]+]]:fpr64 = Select_FPR64_Using_CC_GPR [[ANDI]], $x0, 1, [[COPY1]], [[COPY2]]
; CHECK-NEXT: $f10_d = COPY [[Select_FPR64_Using_CC_GPR]]
; CHECK-NEXT: PseudoRET implicit $f10_d
%0:gprb(s64) = COPY $x10
%1:fprb(s64) = COPY $f10_d
%2:fprb(s64) = COPY $f11_d
%3:gprb(s64) = G_CONSTANT i64 1
%4:gprb(s64) = G_AND %0, %3
%5:fprb(s64) = G_SELECT %4(s64), %1, %2
$f10_d = COPY %5(s64)
PseudoRET implicit $f10_d

...
152 changes: 152 additions & 0 deletions llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-select-rv32.mir
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Original file line number Diff line number Diff line change
@@ -0,0 +1,152 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=regbankselect \
# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefix=RV32I %s

---
name: fp_select_s32
legalized: true
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $x10, $f10_f, $f11_f

; RV32I-LABEL: name: fp_select_s32
; RV32I: liveins: $x10, $f10_f, $f11_f
; RV32I-NEXT: {{ $}}
; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
; RV32I-NEXT: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f10_f
; RV32I-NEXT: [[COPY2:%[0-9]+]]:fprb(s32) = COPY $f11_f
; RV32I-NEXT: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
; RV32I-NEXT: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY]], [[C]]
; RV32I-NEXT: [[SELECT:%[0-9]+]]:fprb(s32) = G_SELECT [[AND]](s32), [[COPY1]], [[COPY2]]
; RV32I-NEXT: $f10_f = COPY [[SELECT]](s32)
; RV32I-NEXT: PseudoRET implicit $f10_f
%3:_(s32) = COPY $x10
%4:_(s32) = COPY $f10_f
%5:_(s32) = COPY $f11_f
%12:_(s32) = G_CONSTANT i32 1
%11:_(s32) = G_AND %3, %12
%10:_(s32) = G_SELECT %11(s32), %4, %5
$f10_f = COPY %10(s32)
PseudoRET implicit $f10_f

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Should we test some cases where one of the operands are from onlyDefinesFP but the other operand can be either?

Should we test some cases where the def is used by instructions that onlyDefineFP?

...
---
name: fp_select_gpr_use_s32
legalized: true
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $x10, $f10_f, $f11_f

; RV32I-LABEL: name: fp_select_gpr_use_s32
; RV32I: liveins: $x10, $f10_f, $f11_f
; RV32I-NEXT: {{ $}}
; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
; RV32I-NEXT: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f10_f
; RV32I-NEXT: [[COPY2:%[0-9]+]]:fprb(s32) = COPY $f11_f
; RV32I-NEXT: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
; RV32I-NEXT: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY]], [[C]]
; RV32I-NEXT: [[SELECT:%[0-9]+]]:fprb(s32) = G_SELECT [[AND]](s32), [[COPY1]], [[COPY2]]
; RV32I-NEXT: $x10 = COPY [[SELECT]](s32)
; RV32I-NEXT: PseudoRET implicit $x10
%3:_(s32) = COPY $x10
%4:_(s32) = COPY $f10_f
%5:_(s32) = COPY $f11_f
%12:_(s32) = G_CONSTANT i32 1
%11:_(s32) = G_AND %3, %12
%10:_(s32) = G_SELECT %11(s32), %4, %5
$x10 = COPY %10(s32)
PseudoRET implicit $x10

...
---
name: fp_select_gpr_def_s32
legalized: true
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $x10, $x11, $f10_f

; RV32I-LABEL: name: fp_select_gpr_def_s32
; RV32I: liveins: $x10, $x11, $f10_f
; RV32I-NEXT: {{ $}}
; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
; RV32I-NEXT: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f10_f
; RV32I-NEXT: [[COPY2:%[0-9]+]]:gprb(s32) = COPY $x11
; RV32I-NEXT: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
; RV32I-NEXT: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY]], [[C]]
; RV32I-NEXT: [[COPY3:%[0-9]+]]:fprb(s32) = COPY [[COPY2]](s32)
; RV32I-NEXT: [[SELECT:%[0-9]+]]:fprb(s32) = G_SELECT [[AND]](s32), [[COPY1]], [[COPY3]]
; RV32I-NEXT: $f10_f = COPY [[SELECT]](s32)
; RV32I-NEXT: PseudoRET implicit $f10_f
%3:_(s32) = COPY $x10
%4:_(s32) = COPY $f10_f
%5:_(s32) = COPY $x11
%12:_(s32) = G_CONSTANT i32 1
%11:_(s32) = G_AND %3, %12
%10:_(s32) = G_SELECT %11(s32), %4, %5
$f10_f = COPY %10(s32)
PseudoRET implicit $f10_f

...
---
name: fp_select_only_fpr_use_s32
legalized: true
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $x10, $x11, $x12

; RV32I-LABEL: name: fp_select_only_fpr_use_s32
; RV32I: liveins: $x10, $x11, $x12
; RV32I-NEXT: {{ $}}
; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11
; RV32I-NEXT: [[COPY2:%[0-9]+]]:gprb(s32) = COPY $x12
; RV32I-NEXT: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
; RV32I-NEXT: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY]], [[C]]
; RV32I-NEXT: [[SELECT:%[0-9]+]]:gprb(s32) = G_SELECT [[AND]](s32), [[COPY1]], [[COPY2]]
; RV32I-NEXT: $f10_f = COPY [[SELECT]](s32)
; RV32I-NEXT: PseudoRET implicit $f10_f
%3:_(s32) = COPY $x10
%4:_(s32) = COPY $x11
%5:_(s32) = COPY $x12
%12:_(s32) = G_CONSTANT i32 1
%11:_(s32) = G_AND %3, %12
%10:_(s32) = G_SELECT %11(s32), %4, %5
$f10_f = COPY %10(s32)
PseudoRET implicit $f10_f

...
---
name: fp_select_only_one_fpr_def_s32
legalized: true
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $x10, $x11, $f10_f

; RV32I-LABEL: name: fp_select_only_one_fpr_def_s32
; RV32I: liveins: $x10, $x11, $f10_f
; RV32I-NEXT: {{ $}}
; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
; RV32I-NEXT: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f10_f
; RV32I-NEXT: [[COPY2:%[0-9]+]]:gprb(s32) = COPY $x11
; RV32I-NEXT: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
; RV32I-NEXT: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY]], [[C]]
; RV32I-NEXT: [[COPY3:%[0-9]+]]:gprb(s32) = COPY [[COPY1]](s32)
; RV32I-NEXT: [[SELECT:%[0-9]+]]:gprb(s32) = G_SELECT [[AND]](s32), [[COPY3]], [[COPY2]]
; RV32I-NEXT: $x10 = COPY [[SELECT]](s32)
; RV32I-NEXT: PseudoRET implicit $x10
%3:_(s32) = COPY $x10
%4:_(s32) = COPY $f10_f
%5:_(s32) = COPY $x11
%12:_(s32) = G_CONSTANT i32 1
%11:_(s32) = G_AND %3, %12
%10:_(s32) = G_SELECT %11(s32), %4, %5
$x10 = COPY %10(s32)
PseudoRET implicit $x10

...
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