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[RISCV][GISel] Support G_ROTL/G_ROTR with Zbb. #72825

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Merged
merged 2 commits into from
Dec 4, 2023
Merged

[RISCV][GISel] Support G_ROTL/G_ROTR with Zbb. #72825

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5e69f15
[RISCV][GISel] Support G_ROTL/G_ROTR with Zbb.
topperc Nov 20, 2023
d6bef06
fixup! Rename Rotate->RotateActions.
topperc Dec 4, 2023
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10 changes: 10 additions & 0 deletions llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2406,6 +2406,16 @@ LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
Observer.changedInstr(MI);
return Legalized;

case TargetOpcode::G_ROTR:
case TargetOpcode::G_ROTL:
if (TypeIdx != 1)
return UnableToLegalize;

Observer.changingInstr(MI);
widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT);
Observer.changedInstr(MI);
return Legalized;

case TargetOpcode::G_SDIV:
case TargetOpcode::G_SREM:
case TargetOpcode::G_SMIN:
Expand Down
22 changes: 22 additions & 0 deletions llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
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Expand Up @@ -104,6 +104,10 @@ class RISCVInstructionSelector : public InstructionSelector {
// Custom renderers for tablegen
void renderNegImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
int OpIdx) const;
void renderImmSubFromXLen(MachineInstrBuilder &MIB, const MachineInstr &MI,
int OpIdx) const;
void renderImmSubFrom32(MachineInstrBuilder &MIB, const MachineInstr &MI,
int OpIdx) const;
void renderImmPlus1(MachineInstrBuilder &MIB, const MachineInstr &MI,
int OpIdx) const;
void renderImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
Expand Down Expand Up @@ -721,6 +725,24 @@ void RISCVInstructionSelector::renderNegImm(MachineInstrBuilder &MIB,
MIB.addImm(-CstVal);
}

void RISCVInstructionSelector::renderImmSubFromXLen(MachineInstrBuilder &MIB,
const MachineInstr &MI,
int OpIdx) const {
assert(MI.getOpcode() == TargetOpcode::G_CONSTANT && OpIdx == -1 &&
"Expected G_CONSTANT");
uint64_t CstVal = MI.getOperand(1).getCImm()->getZExtValue();
MIB.addImm(STI.getXLen() - CstVal);
}

void RISCVInstructionSelector::renderImmSubFrom32(MachineInstrBuilder &MIB,
const MachineInstr &MI,
int OpIdx) const {
assert(MI.getOpcode() == TargetOpcode::G_CONSTANT && OpIdx == -1 &&
"Expected G_CONSTANT");
uint64_t CstVal = MI.getOperand(1).getCImm()->getZExtValue();
MIB.addImm(32 - CstVal);
}

void RISCVInstructionSelector::renderImmPlus1(MachineInstrBuilder &MIB,
const MachineInstr &MI,
int OpIdx) const {
Expand Down
11 changes: 10 additions & 1 deletion llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
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Expand Up @@ -23,6 +23,7 @@

using namespace llvm;
using namespace LegalityPredicates;
using namespace LegalizeMutations;

// Is this type supported by scalar FP arithmetic operations given the current
// subtarget.
Expand Down Expand Up @@ -99,7 +100,15 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)

getActionDefinitionsBuilder({G_FSHL, G_FSHR}).lower();

getActionDefinitionsBuilder({G_ROTL, G_ROTR}).lower();
auto &RotateActions = getActionDefinitionsBuilder({G_ROTL, G_ROTR});
if (ST.hasStdExtZbb()) {
RotateActions.legalFor({{s32, sXLen}, {sXLen, sXLen}});
// Widen s32 rotate amount to s64 so SDAG patterns will match.
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Is this converting the s32 = G_ROT s32 into a s32 = G_ROT s64? I am surprised that SDAG is built on mismatching types for this operation. Do you mind sharing with me why SDAG takes this approach instead of widening both operands to sXLen?

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it's turning s32 = G_ROT s32, s32 to s32 = G_ROT s32, s64. The last operand is the rotate amount.

There's no way to widen the first type and have it still be the same rotate since there would be extra bits.

Shifts and rotates allow the shift/rotate amount to differ from the other type. In SelectionDAG this is controlled by getScalarShiftAmountTy which defaults to pointer size.

The s32 = G_ROT s32, s64 pattern was added to SelectionDAG for my legal i32 work. Prior to that we used a custom RISCVISD::RORW/ROTW node on RV64.

I may ultimately change the scalar shift amount type to s32 for RV64, for both s32 and s64 but I haven't decided yet. Only the lower 5 or 6 bits are used by hardware.

if (ST.is64Bit())
RotateActions.widenScalarIf(all(typeIs(0, s32), typeIs(1, s32)),
changeTo(1, sXLen));
}
RotateActions.lower();

getActionDefinitionsBuilder(G_BITREVERSE).maxScalar(0, sXLen).lower();

Expand Down
10 changes: 9 additions & 1 deletion llvm/lib/Target/RISCV/RISCVGISel.td
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Expand Up @@ -37,6 +37,11 @@ def ImmPlus1 : SDNodeXForm<imm, [{
def GINegImm : GICustomOperandRenderer<"renderNegImm">,
GISDNodeXFormEquiv<NegImm>;

def GIImmSubFromXLen : GICustomOperandRenderer<"renderImmSubFromXLen">,
GISDNodeXFormEquiv<ImmSubFromXLen>;
def GIImmSubFrom32 : GICustomOperandRenderer<"renderImmSubFrom32">,
GISDNodeXFormEquiv<ImmSubFrom32>;

def GIImmPlus1 :
GICustomOperandRenderer<"renderImmPlus1">,
GISDNodeXFormEquiv<ImmPlus1>;
Expand All @@ -56,9 +61,12 @@ def gi_trailing_zero : GICustomOperandRenderer<"renderTrailingZeros">,
// parameter appears to be ignored so this pattern works for both, however we
// should add a LowLevelTypeByHwMode, and use that to define our XLenLLT instead
// here.
def ShiftMaskGI :
def GIShiftMaskXLen :
GIComplexOperandMatcher<s32, "selectShiftMask">,
GIComplexPatternEquiv<shiftMaskXLen>;
def GIShiftMask32 :
GIComplexOperandMatcher<s32, "selectShiftMask">,
GIComplexPatternEquiv<shiftMask32>;

def gi_sh1add_op : GIComplexOperandMatcher<s32, "selectSHXADDOp<1>">,
GIComplexPatternEquiv<sh1add_op>;
Expand Down
94 changes: 94 additions & 0 deletions llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rotate-rv32.mir
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@@ -0,0 +1,94 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -mattr=+zbb -run-pass=instruction-select \
# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s

---
name: rotl_i32
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $x10, $x11

; CHECK-LABEL: name: rotl_i32
; CHECK: liveins: $x10, $x11
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
; CHECK-NEXT: [[ROL:%[0-9]+]]:gpr = ROL [[COPY]], [[COPY1]]
; CHECK-NEXT: $x10 = COPY [[ROL]]
; CHECK-NEXT: PseudoRET implicit $x10
%0:gprb(s32) = COPY $x10
%1:gprb(s32) = COPY $x11
%2:gprb(s32) = G_ROTL %0, %1(s32)
$x10 = COPY %2(s32)
PseudoRET implicit $x10

...
---
name: rotr_i32
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $x10, $x11

; CHECK-LABEL: name: rotr_i32
; CHECK: liveins: $x10, $x11
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
; CHECK-NEXT: [[ROR:%[0-9]+]]:gpr = ROR [[COPY]], [[COPY1]]
; CHECK-NEXT: $x10 = COPY [[ROR]]
; CHECK-NEXT: PseudoRET implicit $x10
%0:gprb(s32) = COPY $x10
%1:gprb(s32) = COPY $x11
%2:gprb(s32) = G_ROTR %0, %1(s32)
$x10 = COPY %2(s32)
PseudoRET implicit $x10

...
---
name: rotl_imm_i32
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $x10

; CHECK-LABEL: name: rotl_imm_i32
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
; CHECK-NEXT: [[RORI:%[0-9]+]]:gpr = RORI [[COPY]], 27
; CHECK-NEXT: $x10 = COPY [[RORI]]
; CHECK-NEXT: PseudoRET implicit $x10
%0:gprb(s32) = COPY $x10
%1:gprb(s32) = G_CONSTANT i32 5
%2:gprb(s32) = G_ROTL %0, %1(s32)
$x10 = COPY %2(s32)
PseudoRET implicit $x10

...
---
name: rotr_imm_i32
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $x10

; CHECK-LABEL: name: rotr_imm_i32
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
; CHECK-NEXT: [[RORI:%[0-9]+]]:gpr = RORI [[COPY]], 5
; CHECK-NEXT: $x10 = COPY [[RORI]]
; CHECK-NEXT: PseudoRET implicit $x10
%0:gprb(s32) = COPY $x10
%1:gprb(s32) = G_CONSTANT i32 5
%2:gprb(s32) = G_ROTR %0, %1(s32)
$x10 = COPY %2(s32)
PseudoRET implicit $x10

...
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