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[RISCV] Add MinimumJumpTableEntries to TuneInfo #72963

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merged 2 commits into from
Nov 23, 2023
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[RISCV] Add MinimumJumpTableEntries to TuneInfo #72963

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5a715e0
[RISCV] Add MinimumJumpTableEntries to TuneInfo
wangpc-pp Nov 21, 2023
04983a6
fixup! [RISCV] Add MinimumJumpTableEntries to TuneInfo
wangpc-pp Nov 23, 2023
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7 changes: 5 additions & 2 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1363,8 +1363,6 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setPrefFunctionAlignment(Subtarget.getPrefFunctionAlignment());
setPrefLoopAlignment(Subtarget.getPrefLoopAlignment());

setMinimumJumpTableEntries(5);

// Jumps are expensive, compared to logic
setJumpIsExpensive();

Expand Down Expand Up @@ -19701,6 +19699,11 @@ bool RISCVTargetLowering::shouldFoldSelectWithSingleBitTest(
return AndMask.ugt(1024);
return TargetLowering::shouldFoldSelectWithSingleBitTest(VT, AndMask);
}

unsigned RISCVTargetLowering::getMinimumJumpTableEntries() const {
return Subtarget.getMinimumJumpTableEntries();
}

namespace llvm::RISCVVIntrinsicsTable {

#define GET_RISCVVIntrinsicsTable_IMPL
Expand Down
2 changes: 2 additions & 0 deletions llvm/lib/Target/RISCV/RISCVISelLowering.h
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Original file line number Diff line number Diff line change
Expand Up @@ -962,6 +962,8 @@ class RISCVTargetLowering : public TargetLowering {

bool shouldFoldSelectWithSingleBitTest(EVT VT,
const APInt &AndMask) const override;

unsigned getMinimumJumpTableEntries() const override;
};

namespace RISCV {
Expand Down
5 changes: 4 additions & 1 deletion llvm/lib/Target/RISCV/RISCVProcessors.td
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Original file line number Diff line number Diff line change
Expand Up @@ -19,14 +19,17 @@ class RISCVTuneInfo {
bits<16> PrefetchDistance = 0;
bits<16> MinPrefetchStride = 1;
bits<32> MaxPrefetchIterationsAhead = -1;

bits<32> MinimumJumpTableEntries = 5;
}

def RISCVTuneInfoTable : GenericTable {
let FilterClass = "RISCVTuneInfo";
let CppTypeName = "RISCVTuneInfo";
let Fields = ["Name", "PrefFunctionAlignment", "PrefLoopAlignment",
"CacheLineSize", "PrefetchDistance",
"MinPrefetchStride", "MaxPrefetchIterationsAhead"];
"MinPrefetchStride", "MaxPrefetchIterationsAhead",
"MinimumJumpTableEntries"];
}

def getRISCVTuneInfo : SearchIndex {
Expand Down
10 changes: 10 additions & 0 deletions llvm/lib/Target/RISCV/RISCVSubtarget.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -57,6 +57,10 @@ static cl::opt<unsigned> RISCVMaxBuildIntsCost(
static cl::opt<bool> UseAA("riscv-use-aa", cl::init(true),
cl::desc("Enable the use of AA during codegen."));

static cl::opt<unsigned> RISCVMinimumJumpTableEntries(
"riscv-min-jump-table-entries", cl::Hidden,
cl::desc("Set minimum number of entries to use a jump table on RISCV"));

void RISCVSubtarget::anchor() {}

RISCVSubtarget &
Expand Down Expand Up @@ -189,3 +193,9 @@ void RISCVSubtarget::getPostRAMutations(
/// Enable use of alias analysis during code generation (during MI
/// scheduling, DAGCombine, etc.).
bool RISCVSubtarget::useAA() const { return UseAA; }

unsigned RISCVSubtarget::getMinimumJumpTableEntries() const {
return RISCVMinimumJumpTableEntries.getNumOccurrences() > 0
? RISCVMinimumJumpTableEntries
: TuneInfo->MinimumJumpTableEntries;
}
4 changes: 4 additions & 0 deletions llvm/lib/Target/RISCV/RISCVSubtarget.h
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Original file line number Diff line number Diff line change
Expand Up @@ -44,6 +44,8 @@ struct RISCVTuneInfo {
uint16_t PrefetchDistance;
uint16_t MinPrefetchStride;
unsigned MaxPrefetchIterationsAhead;

unsigned MinimumJumpTableEntries;
};

#define GET_RISCVTuneInfoTable_DECL
Expand Down Expand Up @@ -270,6 +272,8 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
unsigned getMaxPrefetchIterationsAhead() const override {
return TuneInfo->MaxPrefetchIterationsAhead;
};

unsigned getMinimumJumpTableEntries() const;
};
} // End llvm namespace

Expand Down
276 changes: 276 additions & 0 deletions llvm/test/CodeGen/RISCV/jumptable.ll
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Expand Up @@ -11,6 +11,18 @@
; RUN: | FileCheck %s -check-prefixes=CHECK,RV64I-MEDIUM
; RUN: llc -mtriple=riscv64 -relocation-model=pic -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefixes=CHECK,RV64I-PIC
; RUN: llc -mtriple=riscv32 -code-model=small -verify-machineinstrs -riscv-min-jump-table-entries=7 < %s \
; RUN: | FileCheck %s -check-prefixes=CHECK,RV32I-SMALL-7-ENTRIES
; RUN: llc -mtriple=riscv32 -code-model=medium -verify-machineinstrs -riscv-min-jump-table-entries=7 < %s \
; RUN: | FileCheck %s -check-prefixes=CHECK,RV32I-MEDIUM-7-ENTRIES
; RUN: llc -mtriple=riscv32 -relocation-model=pic -verify-machineinstrs -riscv-min-jump-table-entries=7 < %s \
; RUN: | FileCheck %s -check-prefixes=CHECK,RV32I-PIC-7-ENTRIES
; RUN: llc -mtriple=riscv64 -code-model=small -verify-machineinstrs -riscv-min-jump-table-entries=7 < %s \
; RUN: | FileCheck %s -check-prefixes=CHECK,RV64I-SMALL-7-ENTRIES
; RUN: llc -mtriple=riscv64 -code-model=medium -verify-machineinstrs -riscv-min-jump-table-entries=7 < %s \
; RUN: | FileCheck %s -check-prefixes=CHECK,RV64I-MEDIUM-7-ENTRIES
; RUN: llc -mtriple=riscv64 -relocation-model=pic -verify-machineinstrs -riscv-min-jump-table-entries=7 < %s \
; RUN: | FileCheck %s -check-prefixes=CHECK,RV64I-PIC-7-ENTRIES

define void @below_threshold(i32 signext %in, ptr %out) nounwind {
; CHECK-LABEL: below_threshold:
Expand Down Expand Up @@ -277,6 +289,270 @@ define void @above_threshold(i32 signext %in, ptr %out) nounwind {
; RV64I-PIC-NEXT: sw a0, 0(a1)
; RV64I-PIC-NEXT: .LBB1_9: # %exit
; RV64I-PIC-NEXT: ret
;
; RV32I-SMALL-7-ENTRIES-LABEL: above_threshold:
; RV32I-SMALL-7-ENTRIES: # %bb.0: # %entry
; RV32I-SMALL-7-ENTRIES-NEXT: li a2, 3
; RV32I-SMALL-7-ENTRIES-NEXT: blt a2, a0, .LBB1_5
; RV32I-SMALL-7-ENTRIES-NEXT: # %bb.1: # %entry
; RV32I-SMALL-7-ENTRIES-NEXT: li a2, 1
; RV32I-SMALL-7-ENTRIES-NEXT: beq a0, a2, .LBB1_9
; RV32I-SMALL-7-ENTRIES-NEXT: # %bb.2: # %entry
; RV32I-SMALL-7-ENTRIES-NEXT: li a2, 2
; RV32I-SMALL-7-ENTRIES-NEXT: beq a0, a2, .LBB1_11
; RV32I-SMALL-7-ENTRIES-NEXT: # %bb.3: # %entry
; RV32I-SMALL-7-ENTRIES-NEXT: li a2, 3
; RV32I-SMALL-7-ENTRIES-NEXT: bne a0, a2, .LBB1_14
; RV32I-SMALL-7-ENTRIES-NEXT: # %bb.4: # %bb3
; RV32I-SMALL-7-ENTRIES-NEXT: li a0, 2
; RV32I-SMALL-7-ENTRIES-NEXT: j .LBB1_13
; RV32I-SMALL-7-ENTRIES-NEXT: .LBB1_5: # %entry
; RV32I-SMALL-7-ENTRIES-NEXT: li a2, 4
; RV32I-SMALL-7-ENTRIES-NEXT: beq a0, a2, .LBB1_10
; RV32I-SMALL-7-ENTRIES-NEXT: # %bb.6: # %entry
; RV32I-SMALL-7-ENTRIES-NEXT: li a2, 5
; RV32I-SMALL-7-ENTRIES-NEXT: beq a0, a2, .LBB1_12
; RV32I-SMALL-7-ENTRIES-NEXT: # %bb.7: # %entry
; RV32I-SMALL-7-ENTRIES-NEXT: li a2, 6
; RV32I-SMALL-7-ENTRIES-NEXT: bne a0, a2, .LBB1_14
; RV32I-SMALL-7-ENTRIES-NEXT: # %bb.8: # %bb6
; RV32I-SMALL-7-ENTRIES-NEXT: li a0, 200
; RV32I-SMALL-7-ENTRIES-NEXT: j .LBB1_13
; RV32I-SMALL-7-ENTRIES-NEXT: .LBB1_9: # %bb1
; RV32I-SMALL-7-ENTRIES-NEXT: li a0, 4
; RV32I-SMALL-7-ENTRIES-NEXT: j .LBB1_13
; RV32I-SMALL-7-ENTRIES-NEXT: .LBB1_10: # %bb4
; RV32I-SMALL-7-ENTRIES-NEXT: li a0, 1
; RV32I-SMALL-7-ENTRIES-NEXT: j .LBB1_13
; RV32I-SMALL-7-ENTRIES-NEXT: .LBB1_11: # %bb2
; RV32I-SMALL-7-ENTRIES-NEXT: li a0, 3
; RV32I-SMALL-7-ENTRIES-NEXT: j .LBB1_13
; RV32I-SMALL-7-ENTRIES-NEXT: .LBB1_12: # %bb5
; RV32I-SMALL-7-ENTRIES-NEXT: li a0, 100
; RV32I-SMALL-7-ENTRIES-NEXT: .LBB1_13: # %exit
; RV32I-SMALL-7-ENTRIES-NEXT: sw a0, 0(a1)
; RV32I-SMALL-7-ENTRIES-NEXT: .LBB1_14: # %exit
; RV32I-SMALL-7-ENTRIES-NEXT: ret
;
; RV32I-MEDIUM-7-ENTRIES-LABEL: above_threshold:
; RV32I-MEDIUM-7-ENTRIES: # %bb.0: # %entry
; RV32I-MEDIUM-7-ENTRIES-NEXT: li a2, 3
; RV32I-MEDIUM-7-ENTRIES-NEXT: blt a2, a0, .LBB1_5
; RV32I-MEDIUM-7-ENTRIES-NEXT: # %bb.1: # %entry
; RV32I-MEDIUM-7-ENTRIES-NEXT: li a2, 1
; RV32I-MEDIUM-7-ENTRIES-NEXT: beq a0, a2, .LBB1_9
; RV32I-MEDIUM-7-ENTRIES-NEXT: # %bb.2: # %entry
; RV32I-MEDIUM-7-ENTRIES-NEXT: li a2, 2
; RV32I-MEDIUM-7-ENTRIES-NEXT: beq a0, a2, .LBB1_11
; RV32I-MEDIUM-7-ENTRIES-NEXT: # %bb.3: # %entry
; RV32I-MEDIUM-7-ENTRIES-NEXT: li a2, 3
; RV32I-MEDIUM-7-ENTRIES-NEXT: bne a0, a2, .LBB1_14
; RV32I-MEDIUM-7-ENTRIES-NEXT: # %bb.4: # %bb3
; RV32I-MEDIUM-7-ENTRIES-NEXT: li a0, 2
; RV32I-MEDIUM-7-ENTRIES-NEXT: j .LBB1_13
; RV32I-MEDIUM-7-ENTRIES-NEXT: .LBB1_5: # %entry
; RV32I-MEDIUM-7-ENTRIES-NEXT: li a2, 4
; RV32I-MEDIUM-7-ENTRIES-NEXT: beq a0, a2, .LBB1_10
; RV32I-MEDIUM-7-ENTRIES-NEXT: # %bb.6: # %entry
; RV32I-MEDIUM-7-ENTRIES-NEXT: li a2, 5
; RV32I-MEDIUM-7-ENTRIES-NEXT: beq a0, a2, .LBB1_12
; RV32I-MEDIUM-7-ENTRIES-NEXT: # %bb.7: # %entry
; RV32I-MEDIUM-7-ENTRIES-NEXT: li a2, 6
; RV32I-MEDIUM-7-ENTRIES-NEXT: bne a0, a2, .LBB1_14
; RV32I-MEDIUM-7-ENTRIES-NEXT: # %bb.8: # %bb6
; RV32I-MEDIUM-7-ENTRIES-NEXT: li a0, 200
; RV32I-MEDIUM-7-ENTRIES-NEXT: j .LBB1_13
; RV32I-MEDIUM-7-ENTRIES-NEXT: .LBB1_9: # %bb1
; RV32I-MEDIUM-7-ENTRIES-NEXT: li a0, 4
; RV32I-MEDIUM-7-ENTRIES-NEXT: j .LBB1_13
; RV32I-MEDIUM-7-ENTRIES-NEXT: .LBB1_10: # %bb4
; RV32I-MEDIUM-7-ENTRIES-NEXT: li a0, 1
; RV32I-MEDIUM-7-ENTRIES-NEXT: j .LBB1_13
; RV32I-MEDIUM-7-ENTRIES-NEXT: .LBB1_11: # %bb2
; RV32I-MEDIUM-7-ENTRIES-NEXT: li a0, 3
; RV32I-MEDIUM-7-ENTRIES-NEXT: j .LBB1_13
; RV32I-MEDIUM-7-ENTRIES-NEXT: .LBB1_12: # %bb5
; RV32I-MEDIUM-7-ENTRIES-NEXT: li a0, 100
; RV32I-MEDIUM-7-ENTRIES-NEXT: .LBB1_13: # %exit
; RV32I-MEDIUM-7-ENTRIES-NEXT: sw a0, 0(a1)
; RV32I-MEDIUM-7-ENTRIES-NEXT: .LBB1_14: # %exit
; RV32I-MEDIUM-7-ENTRIES-NEXT: ret
;
; RV32I-PIC-7-ENTRIES-LABEL: above_threshold:
; RV32I-PIC-7-ENTRIES: # %bb.0: # %entry
; RV32I-PIC-7-ENTRIES-NEXT: li a2, 3
; RV32I-PIC-7-ENTRIES-NEXT: blt a2, a0, .LBB1_5
; RV32I-PIC-7-ENTRIES-NEXT: # %bb.1: # %entry
; RV32I-PIC-7-ENTRIES-NEXT: li a2, 1
; RV32I-PIC-7-ENTRIES-NEXT: beq a0, a2, .LBB1_9
; RV32I-PIC-7-ENTRIES-NEXT: # %bb.2: # %entry
; RV32I-PIC-7-ENTRIES-NEXT: li a2, 2
; RV32I-PIC-7-ENTRIES-NEXT: beq a0, a2, .LBB1_11
; RV32I-PIC-7-ENTRIES-NEXT: # %bb.3: # %entry
; RV32I-PIC-7-ENTRIES-NEXT: li a2, 3
; RV32I-PIC-7-ENTRIES-NEXT: bne a0, a2, .LBB1_14
; RV32I-PIC-7-ENTRIES-NEXT: # %bb.4: # %bb3
; RV32I-PIC-7-ENTRIES-NEXT: li a0, 2
; RV32I-PIC-7-ENTRIES-NEXT: j .LBB1_13
; RV32I-PIC-7-ENTRIES-NEXT: .LBB1_5: # %entry
; RV32I-PIC-7-ENTRIES-NEXT: li a2, 4
; RV32I-PIC-7-ENTRIES-NEXT: beq a0, a2, .LBB1_10
; RV32I-PIC-7-ENTRIES-NEXT: # %bb.6: # %entry
; RV32I-PIC-7-ENTRIES-NEXT: li a2, 5
; RV32I-PIC-7-ENTRIES-NEXT: beq a0, a2, .LBB1_12
; RV32I-PIC-7-ENTRIES-NEXT: # %bb.7: # %entry
; RV32I-PIC-7-ENTRIES-NEXT: li a2, 6
; RV32I-PIC-7-ENTRIES-NEXT: bne a0, a2, .LBB1_14
; RV32I-PIC-7-ENTRIES-NEXT: # %bb.8: # %bb6
; RV32I-PIC-7-ENTRIES-NEXT: li a0, 200
; RV32I-PIC-7-ENTRIES-NEXT: j .LBB1_13
; RV32I-PIC-7-ENTRIES-NEXT: .LBB1_9: # %bb1
; RV32I-PIC-7-ENTRIES-NEXT: li a0, 4
; RV32I-PIC-7-ENTRIES-NEXT: j .LBB1_13
; RV32I-PIC-7-ENTRIES-NEXT: .LBB1_10: # %bb4
; RV32I-PIC-7-ENTRIES-NEXT: li a0, 1
; RV32I-PIC-7-ENTRIES-NEXT: j .LBB1_13
; RV32I-PIC-7-ENTRIES-NEXT: .LBB1_11: # %bb2
; RV32I-PIC-7-ENTRIES-NEXT: li a0, 3
; RV32I-PIC-7-ENTRIES-NEXT: j .LBB1_13
; RV32I-PIC-7-ENTRIES-NEXT: .LBB1_12: # %bb5
; RV32I-PIC-7-ENTRIES-NEXT: li a0, 100
; RV32I-PIC-7-ENTRIES-NEXT: .LBB1_13: # %exit
; RV32I-PIC-7-ENTRIES-NEXT: sw a0, 0(a1)
; RV32I-PIC-7-ENTRIES-NEXT: .LBB1_14: # %exit
; RV32I-PIC-7-ENTRIES-NEXT: ret
;
; RV64I-SMALL-7-ENTRIES-LABEL: above_threshold:
; RV64I-SMALL-7-ENTRIES: # %bb.0: # %entry
; RV64I-SMALL-7-ENTRIES-NEXT: li a2, 3
; RV64I-SMALL-7-ENTRIES-NEXT: blt a2, a0, .LBB1_5
; RV64I-SMALL-7-ENTRIES-NEXT: # %bb.1: # %entry
; RV64I-SMALL-7-ENTRIES-NEXT: li a2, 1
; RV64I-SMALL-7-ENTRIES-NEXT: beq a0, a2, .LBB1_9
; RV64I-SMALL-7-ENTRIES-NEXT: # %bb.2: # %entry
; RV64I-SMALL-7-ENTRIES-NEXT: li a2, 2
; RV64I-SMALL-7-ENTRIES-NEXT: beq a0, a2, .LBB1_11
; RV64I-SMALL-7-ENTRIES-NEXT: # %bb.3: # %entry
; RV64I-SMALL-7-ENTRIES-NEXT: li a2, 3
; RV64I-SMALL-7-ENTRIES-NEXT: bne a0, a2, .LBB1_14
; RV64I-SMALL-7-ENTRIES-NEXT: # %bb.4: # %bb3
; RV64I-SMALL-7-ENTRIES-NEXT: li a0, 2
; RV64I-SMALL-7-ENTRIES-NEXT: j .LBB1_13
; RV64I-SMALL-7-ENTRIES-NEXT: .LBB1_5: # %entry
; RV64I-SMALL-7-ENTRIES-NEXT: li a2, 4
; RV64I-SMALL-7-ENTRIES-NEXT: beq a0, a2, .LBB1_10
; RV64I-SMALL-7-ENTRIES-NEXT: # %bb.6: # %entry
; RV64I-SMALL-7-ENTRIES-NEXT: li a2, 5
; RV64I-SMALL-7-ENTRIES-NEXT: beq a0, a2, .LBB1_12
; RV64I-SMALL-7-ENTRIES-NEXT: # %bb.7: # %entry
; RV64I-SMALL-7-ENTRIES-NEXT: li a2, 6
; RV64I-SMALL-7-ENTRIES-NEXT: bne a0, a2, .LBB1_14
; RV64I-SMALL-7-ENTRIES-NEXT: # %bb.8: # %bb6
; RV64I-SMALL-7-ENTRIES-NEXT: li a0, 200
; RV64I-SMALL-7-ENTRIES-NEXT: j .LBB1_13
; RV64I-SMALL-7-ENTRIES-NEXT: .LBB1_9: # %bb1
; RV64I-SMALL-7-ENTRIES-NEXT: li a0, 4
; RV64I-SMALL-7-ENTRIES-NEXT: j .LBB1_13
; RV64I-SMALL-7-ENTRIES-NEXT: .LBB1_10: # %bb4
; RV64I-SMALL-7-ENTRIES-NEXT: li a0, 1
; RV64I-SMALL-7-ENTRIES-NEXT: j .LBB1_13
; RV64I-SMALL-7-ENTRIES-NEXT: .LBB1_11: # %bb2
; RV64I-SMALL-7-ENTRIES-NEXT: li a0, 3
; RV64I-SMALL-7-ENTRIES-NEXT: j .LBB1_13
; RV64I-SMALL-7-ENTRIES-NEXT: .LBB1_12: # %bb5
; RV64I-SMALL-7-ENTRIES-NEXT: li a0, 100
; RV64I-SMALL-7-ENTRIES-NEXT: .LBB1_13: # %exit
; RV64I-SMALL-7-ENTRIES-NEXT: sw a0, 0(a1)
; RV64I-SMALL-7-ENTRIES-NEXT: .LBB1_14: # %exit
; RV64I-SMALL-7-ENTRIES-NEXT: ret
;
; RV64I-MEDIUM-7-ENTRIES-LABEL: above_threshold:
; RV64I-MEDIUM-7-ENTRIES: # %bb.0: # %entry
; RV64I-MEDIUM-7-ENTRIES-NEXT: li a2, 3
; RV64I-MEDIUM-7-ENTRIES-NEXT: blt a2, a0, .LBB1_5
; RV64I-MEDIUM-7-ENTRIES-NEXT: # %bb.1: # %entry
; RV64I-MEDIUM-7-ENTRIES-NEXT: li a2, 1
; RV64I-MEDIUM-7-ENTRIES-NEXT: beq a0, a2, .LBB1_9
; RV64I-MEDIUM-7-ENTRIES-NEXT: # %bb.2: # %entry
; RV64I-MEDIUM-7-ENTRIES-NEXT: li a2, 2
; RV64I-MEDIUM-7-ENTRIES-NEXT: beq a0, a2, .LBB1_11
; RV64I-MEDIUM-7-ENTRIES-NEXT: # %bb.3: # %entry
; RV64I-MEDIUM-7-ENTRIES-NEXT: li a2, 3
; RV64I-MEDIUM-7-ENTRIES-NEXT: bne a0, a2, .LBB1_14
; RV64I-MEDIUM-7-ENTRIES-NEXT: # %bb.4: # %bb3
; RV64I-MEDIUM-7-ENTRIES-NEXT: li a0, 2
; RV64I-MEDIUM-7-ENTRIES-NEXT: j .LBB1_13
; RV64I-MEDIUM-7-ENTRIES-NEXT: .LBB1_5: # %entry
; RV64I-MEDIUM-7-ENTRIES-NEXT: li a2, 4
; RV64I-MEDIUM-7-ENTRIES-NEXT: beq a0, a2, .LBB1_10
; RV64I-MEDIUM-7-ENTRIES-NEXT: # %bb.6: # %entry
; RV64I-MEDIUM-7-ENTRIES-NEXT: li a2, 5
; RV64I-MEDIUM-7-ENTRIES-NEXT: beq a0, a2, .LBB1_12
; RV64I-MEDIUM-7-ENTRIES-NEXT: # %bb.7: # %entry
; RV64I-MEDIUM-7-ENTRIES-NEXT: li a2, 6
; RV64I-MEDIUM-7-ENTRIES-NEXT: bne a0, a2, .LBB1_14
; RV64I-MEDIUM-7-ENTRIES-NEXT: # %bb.8: # %bb6
; RV64I-MEDIUM-7-ENTRIES-NEXT: li a0, 200
; RV64I-MEDIUM-7-ENTRIES-NEXT: j .LBB1_13
; RV64I-MEDIUM-7-ENTRIES-NEXT: .LBB1_9: # %bb1
; RV64I-MEDIUM-7-ENTRIES-NEXT: li a0, 4
; RV64I-MEDIUM-7-ENTRIES-NEXT: j .LBB1_13
; RV64I-MEDIUM-7-ENTRIES-NEXT: .LBB1_10: # %bb4
; RV64I-MEDIUM-7-ENTRIES-NEXT: li a0, 1
; RV64I-MEDIUM-7-ENTRIES-NEXT: j .LBB1_13
; RV64I-MEDIUM-7-ENTRIES-NEXT: .LBB1_11: # %bb2
; RV64I-MEDIUM-7-ENTRIES-NEXT: li a0, 3
; RV64I-MEDIUM-7-ENTRIES-NEXT: j .LBB1_13
; RV64I-MEDIUM-7-ENTRIES-NEXT: .LBB1_12: # %bb5
; RV64I-MEDIUM-7-ENTRIES-NEXT: li a0, 100
; RV64I-MEDIUM-7-ENTRIES-NEXT: .LBB1_13: # %exit
; RV64I-MEDIUM-7-ENTRIES-NEXT: sw a0, 0(a1)
; RV64I-MEDIUM-7-ENTRIES-NEXT: .LBB1_14: # %exit
; RV64I-MEDIUM-7-ENTRIES-NEXT: ret
;
; RV64I-PIC-7-ENTRIES-LABEL: above_threshold:
; RV64I-PIC-7-ENTRIES: # %bb.0: # %entry
; RV64I-PIC-7-ENTRIES-NEXT: li a2, 3
; RV64I-PIC-7-ENTRIES-NEXT: blt a2, a0, .LBB1_5
; RV64I-PIC-7-ENTRIES-NEXT: # %bb.1: # %entry
; RV64I-PIC-7-ENTRIES-NEXT: li a2, 1
; RV64I-PIC-7-ENTRIES-NEXT: beq a0, a2, .LBB1_9
; RV64I-PIC-7-ENTRIES-NEXT: # %bb.2: # %entry
; RV64I-PIC-7-ENTRIES-NEXT: li a2, 2
; RV64I-PIC-7-ENTRIES-NEXT: beq a0, a2, .LBB1_11
; RV64I-PIC-7-ENTRIES-NEXT: # %bb.3: # %entry
; RV64I-PIC-7-ENTRIES-NEXT: li a2, 3
; RV64I-PIC-7-ENTRIES-NEXT: bne a0, a2, .LBB1_14
; RV64I-PIC-7-ENTRIES-NEXT: # %bb.4: # %bb3
; RV64I-PIC-7-ENTRIES-NEXT: li a0, 2
; RV64I-PIC-7-ENTRIES-NEXT: j .LBB1_13
; RV64I-PIC-7-ENTRIES-NEXT: .LBB1_5: # %entry
; RV64I-PIC-7-ENTRIES-NEXT: li a2, 4
; RV64I-PIC-7-ENTRIES-NEXT: beq a0, a2, .LBB1_10
; RV64I-PIC-7-ENTRIES-NEXT: # %bb.6: # %entry
; RV64I-PIC-7-ENTRIES-NEXT: li a2, 5
; RV64I-PIC-7-ENTRIES-NEXT: beq a0, a2, .LBB1_12
; RV64I-PIC-7-ENTRIES-NEXT: # %bb.7: # %entry
; RV64I-PIC-7-ENTRIES-NEXT: li a2, 6
; RV64I-PIC-7-ENTRIES-NEXT: bne a0, a2, .LBB1_14
; RV64I-PIC-7-ENTRIES-NEXT: # %bb.8: # %bb6
; RV64I-PIC-7-ENTRIES-NEXT: li a0, 200
; RV64I-PIC-7-ENTRIES-NEXT: j .LBB1_13
; RV64I-PIC-7-ENTRIES-NEXT: .LBB1_9: # %bb1
; RV64I-PIC-7-ENTRIES-NEXT: li a0, 4
; RV64I-PIC-7-ENTRIES-NEXT: j .LBB1_13
; RV64I-PIC-7-ENTRIES-NEXT: .LBB1_10: # %bb4
; RV64I-PIC-7-ENTRIES-NEXT: li a0, 1
; RV64I-PIC-7-ENTRIES-NEXT: j .LBB1_13
; RV64I-PIC-7-ENTRIES-NEXT: .LBB1_11: # %bb2
; RV64I-PIC-7-ENTRIES-NEXT: li a0, 3
; RV64I-PIC-7-ENTRIES-NEXT: j .LBB1_13
; RV64I-PIC-7-ENTRIES-NEXT: .LBB1_12: # %bb5
; RV64I-PIC-7-ENTRIES-NEXT: li a0, 100
; RV64I-PIC-7-ENTRIES-NEXT: .LBB1_13: # %exit
; RV64I-PIC-7-ENTRIES-NEXT: sw a0, 0(a1)
; RV64I-PIC-7-ENTRIES-NEXT: .LBB1_14: # %exit
; RV64I-PIC-7-ENTRIES-NEXT: ret
entry:
switch i32 %in, label %exit [
i32 1, label %bb1
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