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[bolt] Support arm64 FP register spills #73021

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Dec 5, 2023
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6 changes: 6 additions & 0 deletions bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -314,6 +314,12 @@ class AArch64MCPlusBuilder : public MCPlusBuilder {

bool isRegToRegMove(const MCInst &Inst, MCPhysReg &From,
MCPhysReg &To) const override {
if (Inst.getOpcode() == AArch64::FMOVDXr) {
From = Inst.getOperand(1).getReg();
To = Inst.getOperand(0).getReg();
return true;
}
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new line please after }


if (Inst.getOpcode() != AArch64::ORRXrs)
return false;
if (Inst.getOperand(1).getReg() != AArch64::XZR)
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19 changes: 19 additions & 0 deletions bolt/test/AArch64/fp-reg-spill.s
Original file line number Diff line number Diff line change
@@ -0,0 +1,19 @@
# Check that we correctly handle arm64 fp register spills in
# bolt when we are processing jump tables.
Comment on lines +1 to +2
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Sorry for jumping in late after the change landed. This test checks that BOLT doesn't crash, but it doesn't really check for the correct handling of the jump table. You'll need to add FileCheck checks for --print-cfg dumps or other checks for the output.

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The idea behind the test was not to check the jump table (although it would be nice), but the previous bolt assertion during analyzation. So the test is good-enough I think

# REQUIRES: system-linux
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Please add test scription at the beginning of the file

# RUN: llvm-mc -filetype=obj -triple=aarch64 %s -o %t.o
# RUN: ld.lld --emit-relocs %t.o -o %t.elf
# RUN: llvm-bolt --jump-tables=move %t.elf -o %t.bolt

.globl _foo, _start

_foo:
ret

_start:
adr x6, _foo
fmov d18,x6
fmov x5,d18
ldrb w5, [x5, w1, uxtw]
add x5, x6, w5, sxtb #2
br x5