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[X86] Fix optmasks handling for AVX10.1-256 #73074

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[X86] Fix optmasks handling for AVX10.1-256 #73074

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35 changes: 14 additions & 21 deletions llvm/lib/Target/X86/X86DomainReassignment.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -662,37 +662,30 @@ void X86DomainReassignment::initConverters() {

if (STI->hasBWI()) {
createReplacer(X86::MOV32rm, HasEGPR ? X86::KMOVDkm_EVEX : X86::KMOVDkm);
createReplacer(X86::MOV64rm, HasEGPR ? X86::KMOVQkm_EVEX : X86::KMOVQkm);

createReplacer(X86::MOV32mr, HasEGPR ? X86::KMOVDmk_EVEX : X86::KMOVDmk);
createReplacer(X86::MOV64mr, HasEGPR ? X86::KMOVQmk_EVEX : X86::KMOVQmk);

createReplacer(X86::MOV32rr, HasEGPR ? X86::KMOVDkk_EVEX : X86::KMOVDkk);
createReplacer(X86::MOV64rr, HasEGPR ? X86::KMOVQkk_EVEX : X86::KMOVQkk);

createReplacer(X86::SHR32ri, X86::KSHIFTRDri);
createReplacer(X86::SHR64ri, X86::KSHIFTRQri);

createReplacer(X86::SHL32ri, X86::KSHIFTLDri);
createReplacer(X86::SHL64ri, X86::KSHIFTLQri);

createReplacer(X86::ADD32rr, X86::KADDDrr);
createReplacer(X86::ADD64rr, X86::KADDQrr);

createReplacer(X86::NOT32r, X86::KNOTDrr);
createReplacer(X86::NOT64r, X86::KNOTQrr);

createReplacer(X86::OR32rr, X86::KORDrr);
createReplacer(X86::OR64rr, X86::KORQrr);

createReplacer(X86::AND32rr, X86::KANDDrr);
createReplacer(X86::AND64rr, X86::KANDQrr);

createReplacer(X86::ANDN32rr, X86::KANDNDrr);
createReplacer(X86::ANDN64rr, X86::KANDNQrr);

createReplacer(X86::XOR32rr, X86::KXORDrr);
createReplacer(X86::XOR64rr, X86::KXORQrr);

if (STI->hasEVEX512()) {
createReplacer(X86::MOV64rm, HasEGPR ? X86::KMOVQkm_EVEX : X86::KMOVQkm);
createReplacer(X86::MOV64mr, HasEGPR ? X86::KMOVQmk_EVEX : X86::KMOVQmk);
createReplacer(X86::MOV64rr, HasEGPR ? X86::KMOVQkk_EVEX : X86::KMOVQkk);
createReplacer(X86::SHR64ri, X86::KSHIFTRQri);
createReplacer(X86::SHL64ri, X86::KSHIFTLQri);
createReplacer(X86::ADD64rr, X86::KADDQrr);
createReplacer(X86::NOT64r, X86::KNOTQrr);
createReplacer(X86::OR64rr, X86::KORQrr);
createReplacer(X86::AND64rr, X86::KANDQrr);
createReplacer(X86::ANDN64rr, X86::KANDNQrr);
createReplacer(X86::XOR64rr, X86::KXORQrr);
}

// TODO: KTEST is not a replacement for TEST due to flag differences. Need
// to prove only Z flag is used.
Expand Down
5 changes: 4 additions & 1 deletion llvm/lib/Target/X86/X86ISelLowering.cpp
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Expand Up @@ -2058,9 +2058,12 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
// AVX512BW..
if (!Subtarget.useSoftFloat() && Subtarget.hasBWI()) {
addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
if (Subtarget.hasEVEX512())
addRegisterClass(MVT::v64i1, &X86::VK64RegClass);

for (auto VT : { MVT::v32i1, MVT::v64i1 }) {
if (VT == MVT::v64i1 && !Subtarget.hasEVEX512())
continue;
setOperationAction(ISD::VSELECT, VT, Expand);
setOperationAction(ISD::TRUNCATE, VT, Custom);
setOperationAction(ISD::SETCC, VT, Custom);
Expand Down
16 changes: 10 additions & 6 deletions llvm/lib/Target/X86/X86InstrInfo.cpp
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Expand Up @@ -3996,7 +3996,8 @@ static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg,
// anyone.
if (X86::VK16RegClass.contains(SrcReg)) {
if (X86::GR64RegClass.contains(DestReg)) {
assert(Subtarget.hasBWI());
assert(Subtarget.hasBWI() && Subtarget.hasEVEX512() &&
"KMOVQ requires BWI with EVEX512");
return HasEGPR ? X86::KMOVQrk_EVEX : X86::KMOVQrk;
}
if (X86::GR32RegClass.contains(DestReg))
Expand All @@ -4011,7 +4012,8 @@ static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg,
// anyone.
if (X86::VK16RegClass.contains(DestReg)) {
if (X86::GR64RegClass.contains(SrcReg)) {
assert(Subtarget.hasBWI());
assert(Subtarget.hasBWI() && Subtarget.hasEVEX512() &&
"KMOVQ requires BWI with EVEX512");
return HasEGPR ? X86::KMOVQkr_EVEX : X86::KMOVQkr;
}
if (X86::GR32RegClass.contains(SrcReg))
Expand Down Expand Up @@ -4125,8 +4127,9 @@ void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
// All KMASK RegClasses hold the same k registers, can be tested against
// anyone.
else if (X86::VK16RegClass.contains(DestReg, SrcReg))
Opc = Subtarget.hasBWI() ? (HasEGPR ? X86::KMOVQkk_EVEX : X86::KMOVQkk)
: (HasEGPR ? X86::KMOVQkk_EVEX : X86::KMOVWkk);
Opc = Subtarget.hasBWI() && Subtarget.hasEVEX512()
? (HasEGPR ? X86::KMOVQkk_EVEX : X86::KMOVQkk)
: (HasEGPR ? X86::KMOVQkk_EVEX : X86::KMOVWkk);
if (!Opc)
Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, Subtarget);

Expand Down Expand Up @@ -4247,7 +4250,8 @@ static unsigned getLoadStoreRegOpcode(Register Reg,
if (X86::RFP64RegClass.hasSubClassEq(RC))
return Load ? X86::LD_Fp64m : X86::ST_Fp64m;
if (X86::VK64RegClass.hasSubClassEq(RC)) {
assert(STI.hasBWI() && "KMOVQ requires BWI");
assert(STI.hasBWI() && STI.hasEVEX512() &&
"KMOVQ requires BWI with EVEX512");
return Load ? (HasEGPR ? X86::KMOVQkm_EVEX : X86::KMOVQkm)
: (HasEGPR ? X86::KMOVQmk_EVEX : X86::KMOVQmk);
}
Expand Down Expand Up @@ -10523,7 +10527,7 @@ void X86InstrInfo::buildClearRegister(Register Reg, MachineBasicBlock &MBB,
return;

// KXOR is safe to use because it doesn't affect flags.
unsigned Op = ST.hasBWI() ? X86::KXORQrr : X86::KXORWrr;
unsigned Op = ST.hasBWI() && ST.hasEVEX512() ? X86::KXORQrr : X86::KXORWrr;
BuildMI(MBB, Iter, DL, get(Op), Reg)
.addReg(Reg, RegState::Undef)
.addReg(Reg, RegState::Undef);
Expand Down
3 changes: 2 additions & 1 deletion llvm/lib/Target/X86/X86Subtarget.h
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Expand Up @@ -244,7 +244,8 @@ class X86Subtarget final : public X86GenSubtargetInfo {
// TODO: Currently we're always allowing widening on CPUs without VLX,
// because for many cases we don't have a better option.
bool canExtendTo512DQ() const {
return hasAVX512() && (!hasVLX() || getPreferVectorWidth() >= 512);
return hasAVX512() && (!hasVLX() || getPreferVectorWidth() >= 512) &&
hasEVEX512();
}
bool canExtendTo512BW() const {
return hasBWI() && canExtendTo512DQ();
Expand Down
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