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[RISCV][GISel] Select trap and debugtrap. #73171

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Merged
merged 4 commits into from
Nov 27, 2023
Merged

[RISCV][GISel] Select trap and debugtrap. #73171

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c992992
[RISCV][GISel] Select trap and debugtrap.
topperc Nov 22, 2023
7eaa822
fixup! Use MI instead of I for consistency with rest of file.
topperc Nov 22, 2023
9b17799
fixup! Add const to selectIntrinsicWithSideEffects
topperc Nov 23, 2023
ae0f218
fixup! Add assert.
topperc Nov 27, 2023
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27 changes: 27 additions & 0 deletions llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -72,6 +72,8 @@ class RISCVInstructionSelector : public InstructionSelector {
MachineRegisterInfo &MRI) const;
bool selectFPCompare(MachineInstr &MI, MachineIRBuilder &MIB,
MachineRegisterInfo &MRI) const;
bool selectIntrinsicWithSideEffects(MachineInstr &MI, MachineIRBuilder &MIB,
MachineRegisterInfo &MRI) const;

ComplexRendererFns selectShiftMask(MachineOperand &Root) const;
ComplexRendererFns selectAddrRegImm(MachineOperand &Root) const;
Expand Down Expand Up @@ -564,6 +566,8 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) {
return selectSelect(MI, MIB, MRI);
case TargetOpcode::G_FCMP:
return selectFPCompare(MI, MIB, MRI);
case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS:
return selectIntrinsicWithSideEffects(MI, MIB, MRI);
default:
return false;
}
Expand Down Expand Up @@ -1099,6 +1103,29 @@ bool RISCVInstructionSelector::selectFPCompare(MachineInstr &MI,
return true;
}

bool RISCVInstructionSelector::selectIntrinsicWithSideEffects(
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assert (TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS);

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Doesn't the cast to GIntrinsic already take care of that?

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I think it will pass in the G_INTRINSIC, G_INTRINSIC_CONVERGENT, and G_INTRINSIC_CONVERGENT_W_WIDE_EFFECTS too, but it shouldn't.

MachineInstr &MI, MachineIRBuilder &MIB, MachineRegisterInfo &MRI) const {
assert(MI.getOpcode() == TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS &&
"Unexpected opcode");
// Find the intrinsic ID.
unsigned IntrinID = cast<GIntrinsic>(MI).getIntrinsicID();

// Select the instruction.
switch (IntrinID) {
default:
return false;
case Intrinsic::trap:
MIB.buildInstr(RISCV::UNIMP, {}, {});
break;
case Intrinsic::debugtrap:
MIB.buildInstr(RISCV::EBREAK, {}, {});
break;
}

MI.eraseFromParent();
return true;
}

namespace llvm {
InstructionSelector *
createRISCVInstructionSelector(const RISCVTargetMachine &TM,
Expand Down
34 changes: 34 additions & 0 deletions llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/trap.mir
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@@ -0,0 +1,34 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -run-pass=instruction-select -simplify-mir \
# RUN: -verify-machineinstrs %s -o - | FileCheck %s
# RUN: llc -mtriple=riscv64 -run-pass=instruction-select -simplify-mir \
# RUN: -verify-machineinstrs %s -o - | FileCheck %s

---
name: test_trap
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1:
; CHECK-LABEL: name: test_trap
; CHECK: UNIMP
; CHECK-NEXT: PseudoRET
G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.trap)
PseudoRET

...
---
name: test_debugtrap
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1:
; CHECK-LABEL: name: test_debugtrap
; CHECK: EBREAK
; CHECK-NEXT: PseudoRET
G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.debugtrap)
PseudoRET

...