Skip to content

[SelectionDAG] Add space-optimized forms of OPC_EmitCopyToReg #73293

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 3 commits into from
Dec 12, 2023
Merged

[SelectionDAG] Add space-optimized forms of OPC_EmitCopyToReg #73293

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
3 commits
Select commit Hold shift + click to select a range
d9517fb
[SelectionDAG] Add space-optimized forms of OPC_EmitCopyToReg
wangpc-pp Nov 24, 2023
92a30ec
Half -> TwoByte
wangpc-pp Nov 24, 2023
0e9e102
format
wangpc-pp Nov 24, 2023
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
8 changes: 8 additions & 0 deletions llvm/include/llvm/CodeGen/SelectionDAGISel.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -199,7 +199,15 @@ class SelectionDAGISel : public MachineFunctionPass {
OPC_EmitMergeInputChains1_1,
OPC_EmitMergeInputChains1_2,
OPC_EmitCopyToReg,
OPC_EmitCopyToReg0,
OPC_EmitCopyToReg1,
OPC_EmitCopyToReg2,
OPC_EmitCopyToReg3,
OPC_EmitCopyToReg4,
OPC_EmitCopyToReg5,
OPC_EmitCopyToReg6,
OPC_EmitCopyToReg7,
OPC_EmitCopyToRegTwoByte,
OPC_EmitNodeXForm,
OPC_EmitNode,
// Space-optimized forms that implicitly encode number of result VTs.
Expand Down
17 changes: 14 additions & 3 deletions llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -3610,11 +3610,22 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
}

case OPC_EmitCopyToReg:
case OPC_EmitCopyToReg2: {
unsigned RecNo = MatcherTable[MatcherIndex++];
case OPC_EmitCopyToReg0:
case OPC_EmitCopyToReg1:
case OPC_EmitCopyToReg2:
case OPC_EmitCopyToReg3:
case OPC_EmitCopyToReg4:
case OPC_EmitCopyToReg5:
case OPC_EmitCopyToReg6:
case OPC_EmitCopyToReg7:
case OPC_EmitCopyToRegTwoByte: {
unsigned RecNo =
Opcode >= OPC_EmitCopyToReg0 && Opcode <= OPC_EmitCopyToReg7
? Opcode - OPC_EmitCopyToReg0
: MatcherTable[MatcherIndex++];
assert(RecNo < RecordedNodes.size() && "Invalid EmitCopyToReg");
unsigned DestPhysReg = MatcherTable[MatcherIndex++];
if (Opcode == OPC_EmitCopyToReg2)
if (Opcode == OPC_EmitCopyToRegTwoByte)
DestPhysReg |= MatcherTable[MatcherIndex++] << 8;

if (!InputChain.getNode())
Expand Down
12 changes: 9 additions & 3 deletions llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -755,14 +755,20 @@ EmitMatcher(const Matcher *N, const unsigned Indent, unsigned CurrentIdx,
const auto *C2RMatcher = cast<EmitCopyToRegMatcher>(N);
int Bytes = 3;
const CodeGenRegister *Reg = C2RMatcher->getDestPhysReg();
unsigned Slot = C2RMatcher->getSrcSlot();
if (Reg->EnumValue > 255) {
assert(isUInt<16>(Reg->EnumValue) && "not handled");
OS << "OPC_EmitCopyToReg2, " << C2RMatcher->getSrcSlot() << ", "
OS << "OPC_EmitCopyToRegTwoByte, " << Slot << ", "
<< "TARGET_VAL(" << getQualifiedName(Reg->TheDef) << "),\n";
++Bytes;
} else {
OS << "OPC_EmitCopyToReg, " << C2RMatcher->getSrcSlot() << ", "
<< getQualifiedName(Reg->TheDef) << ",\n";
if (Slot < 8) {
OS << "OPC_EmitCopyToReg" << Slot << ", "
<< getQualifiedName(Reg->TheDef) << ",\n";
--Bytes;
} else
OS << "OPC_EmitCopyToReg, " << Slot << ", "
<< getQualifiedName(Reg->TheDef) << ",\n";
}

return Bytes;
Expand Down