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Dec 15, 2023
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[clang][RISCV] Change default abi with f extension but without d extension #73489

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3 changes: 3 additions & 0 deletions clang/docs/ReleaseNotes.rst
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Expand Up @@ -954,6 +954,9 @@ RISC-V Support
- Unaligned memory accesses can be toggled by ``-m[no-]unaligned-access`` or the
aliases ``-m[no-]strict-align``.

- Default ABI with F but without D was changed to ilp32f for RV32 and to lp64f
for RV64.

CUDA/HIP Language Changes
^^^^^^^^^^^^^^^^^^^^^^^^^

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14 changes: 9 additions & 5 deletions clang/test/Driver/riscv-abi.c
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Expand Up @@ -4,8 +4,6 @@
// RUN: | FileCheck -check-prefix=CHECK-ILP32 %s
// RUN: %clang --target=riscv32-unknown-elf %s -### -march=rv32imc 2>&1 \
// RUN: | FileCheck -check-prefix=CHECK-ILP32 %s
// RUN: %clang --target=riscv32-unknown-elf %s -### -march=rv32imf 2>&1 \
// RUN: | FileCheck -check-prefix=CHECK-ILP32 %s
// RUN: %clang --target=riscv32-unknown-elf -x assembler %s -### 2>&1 \
// RUN: | FileCheck -check-prefix=CHECK-ILP32 %s
// RUN: %clang --target=riscv32-unknown-elf -x assembler %s -### \
Expand All @@ -24,6 +22,10 @@

// RUN: %clang --target=riscv32-unknown-elf %s -### -march=rv32if -mabi=ilp32f 2>&1 \
// RUN: | FileCheck -check-prefix=CHECK-ILP32F %s
// RUN: %clang --target=riscv32-unknown-elf %s -### -mabi=ilp32f 2>&1 \
// RUN: | FileCheck -check-prefix=CHECK-ILP32F %s
// RUN: %clang --target=riscv32-unknown-elf %s -### -march=rv32if 2>&1 \
// RUN: | FileCheck -check-prefix=CHECK-ILP32F %s

// CHECK-ILP32F: "-target-abi" "ilp32f"

Expand Down Expand Up @@ -51,16 +53,18 @@
// RUN: | FileCheck -check-prefix=CHECK-LP64 %s
// RUN: %clang --target=riscv64-unknown-elf %s -### -march=rv64imc 2>&1 \
// RUN: | FileCheck -check-prefix=CHECK-LP64 %s
// RUN: %clang --target=riscv64-unknown-elf %s -### -march=rv64imf 2>&1 \
// RUN: | FileCheck -check-prefix=CHECK-LP64 %s
// RUN: %clang --target=riscv64-unknown-elf -x assembler %s -### 2>&1 \
// RUN: | FileCheck -check-prefix=CHECK-LP64 %s
// RUN: %clang --target=riscv64-unknown-elf -x assembler %s -### \
// RUN: -mabi=lp64 2>&1 | FileCheck -check-prefix=CHECK-LP64 %s

// CHECK-LP64: "-target-abi" "lp64"

// RUN: not %clang --target=riscv64-unknown-elf %s -### -march=rv64f -mabi=lp64f 2>&1 \
// RUN: %clang --target=riscv64-unknown-elf %s -### -march=rv64if -mabi=lp64f 2>&1 \
// RUN: | FileCheck -check-prefix=CHECK-LP64F %s
// RUN: %clang --target=riscv64-unknown-elf %s -### -mabi=lp64f 2>&1 \
// RUN: | FileCheck -check-prefix=CHECK-LP64F %s
// RUN: %clang --target=riscv64-unknown-elf %s -### -march=rv64if 2>&1 \
// RUN: | FileCheck -check-prefix=CHECK-LP64F %s

// CHECK-LP64F: "-target-abi" "lp64f"
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6 changes: 3 additions & 3 deletions clang/test/Driver/riscv-cpus.c
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Expand Up @@ -113,15 +113,15 @@
// MCPU-SIFIVE-E24: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f"
// MCPU-SIFIVE-E24: "-target-feature" "+c"
// MCPU-SIFIVE-E24: "-target-feature" "+zicsr" "-target-feature" "+zifencei"
// MCPU-SIFIVE-E24: "-target-abi" "ilp32"
// MCPU-SIFIVE-E24: "-target-abi" "ilp32f"

// mcpu with default march
// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-e34 | FileCheck -check-prefix=MCPU-SIFIVE-E34 %s
// MCPU-SIFIVE-E34: "-nostdsysteminc" "-target-cpu" "sifive-e34"
// MCPU-SIFIVE-E34: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f"
// MCPU-SIFIVE-E34: "-target-feature" "+c"
// MCPU-SIFIVE-E34: "-target-feature" "+zicsr" "-target-feature" "+zifencei"
// MCPU-SIFIVE-E34: "-target-abi" "ilp32"
// MCPU-SIFIVE-E34: "-target-abi" "ilp32f"

// mcpu with mabi option
// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-s21 -mabi=lp64 | FileCheck -check-prefix=MCPU-ABI-SIFIVE-S21 %s
Expand Down Expand Up @@ -178,7 +178,7 @@
// MCPU-SIFIVE-E76: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f"
// MCPU-SIFIVE-E76: "-target-feature" "+c"
// MCPU-SIFIVE-E76: "-target-feature" "+zicsr" "-target-feature" "+zifencei"
// MCPU-SIFIVE-E76: "-target-abi" "ilp32"
// MCPU-SIFIVE-E76: "-target-abi" "ilp32f"

// mcpu with mabi option
// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-u74 -mabi=lp64 | FileCheck -check-prefix=MCPU-ABI-SIFIVE-U74 %s
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1 change: 1 addition & 0 deletions llvm/docs/ReleaseNotes.rst
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Expand Up @@ -133,6 +133,7 @@ Changes to the RISC-V Backend
* The Zfa extension version was upgraded to 1.0 and is no longer experimental.
* Zihintntl extension version was upgraded to 1.0 and is no longer experimental.
* Intrinsics were added for Zk*, Zbb, and Zbc. See https://github.com/riscv-non-isa/riscv-c-api-doc/blob/master/riscv-c-api.md#scalar-bit-manipulation-extension-intrinsics
* Default ABI with F but without D was changed to ilp32f for RV32 and to lp64f for RV64.

Changes to the WebAssembly Backend
----------------------------------
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4 changes: 4 additions & 0 deletions llvm/lib/Support/RISCVISAInfo.cpp
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Expand Up @@ -1292,12 +1292,16 @@ StringRef RISCVISAInfo::computeDefaultABI() const {
if (XLen == 32) {
if (hasExtension("d"))
return "ilp32d";
if (hasExtension("f"))
return "ilp32f";
if (hasExtension("e"))
return "ilp32e";
return "ilp32";
} else if (XLen == 64) {
if (hasExtension("d"))
return "lp64d";
if (hasExtension("f"))
return "lp64f";
if (hasExtension("e"))
return "lp64e";
return "lp64";
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4 changes: 2 additions & 2 deletions llvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll
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@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=ILP32
; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=LP64
; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32f -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=ILP32F
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4 changes: 2 additions & 2 deletions llvm/test/CodeGen/RISCV/calling-conv-half.ll
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@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV32I
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV64I
; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV32IF
; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV64IF
; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi=ilp32 -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV32IF
; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi=lp64 -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV64IF
; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi=ilp32f -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV32-ILP32F
; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi=lp64f -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV64-LP64F
; RUN: llc -mtriple=riscv32 -mattr=+f,+zfhmin -target-abi=ilp32f -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV32-ILP32ZFHMIN
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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/RISCV/calling-conv-rv32f-ilp32.ll
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@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi=ilp32 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32IF

; Exercises the ILP32 calling convention code in the case that f32 is a legal
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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/RISCV/calling-conv-vector-float.ll
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@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi=lp64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64 %s
; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi=lp64f -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64LP64F %s
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8 changes: 4 additions & 4 deletions llvm/test/CodeGen/RISCV/float-bitmanip-dagcombines.ll
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@@ -1,15 +1,15 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I %s
; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
; RUN: llc -mtriple=riscv32 -target-abi ilp32 -mattr=+f -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32IF %s
; RUN: llc -mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs < %s \
; RUN: llc -mtriple=riscv32 -target-abi ilp32 -mattr=+zfinx -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32IZFINX %s
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64I %s
; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
; RUN: llc -mtriple=riscv64 -target-abi lp64 -mattr=+f -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64IF %s
; RUN: llc -mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs < %s \
; RUN: llc -mtriple=riscv64 -target-abi lp64 -mattr=+zfinx -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64IZFINX %s

; This file tests cases where simple floating point operations can be
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7 changes: 1 addition & 6 deletions llvm/test/CodeGen/RISCV/float-frem.ll
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Expand Up @@ -19,12 +19,7 @@ define float @frem_f32(float %a, float %b) nounwind {
;
; RV64IF-LABEL: frem_f32:
; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: call fmodf@plt
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
; RV64IF-NEXT: tail fmodf@plt
;
; RV32IZFINX-LABEL: frem_f32:
; RV32IZFINX: # %bb.0:
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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/RISCV/float-select-verify.ll
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@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+f -stop-after=finalize-isel < %s | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64 -stop-after=finalize-isel < %s | FileCheck %s

define dso_local void @buz(i1 %pred, float %a, float %b) {
; CHECK-LABEL: name: buz
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18 changes: 9 additions & 9 deletions llvm/test/CodeGen/RISCV/half-bitmanip-dagcombines.ll
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@@ -1,25 +1,25 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I %s
; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
; RUN: llc -mtriple=riscv32 -target-abi ilp32 -mattr=+zfh -verify-machineinstrs \
; RUN: < %s | FileCheck -check-prefix=RV32IZFH %s
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64I %s
; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
; RUN: llc -mtriple=riscv64 -target-abi lp64 -mattr=+zfh -verify-machineinstrs \
; RUN: < %s | FileCheck -check-prefix=RV64IZFH %s
; RUN: llc -mtriple=riscv32 -mattr=+zhinx -verify-machineinstrs \
; RUN: llc -mtriple=riscv32 -target-abi ilp32 -mattr=+zhinx -verify-machineinstrs \
; RUN: < %s | FileCheck -check-prefix=RV32IZHINX %s
; RUN: llc -mtriple=riscv64 -mattr=+zhinx -verify-machineinstrs \
; RUN: llc -mtriple=riscv64 -target-abi lp64 -mattr=+zhinx -verify-machineinstrs \
; RUN: < %s | FileCheck -check-prefix=RV64IZHINX %s
; RUN: llc -mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs \
; RUN: llc -mtriple=riscv32 -target-abi ilp32 -mattr=+zfhmin -verify-machineinstrs \
; RUN: < %s | FileCheck -check-prefix=RV32IZFHMIN %s
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: llc -mtriple=riscv64 -target-abi lp64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64I %s
; RUN: llc -mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs \
; RUN: llc -mtriple=riscv64 -target-abi lp64 -mattr=+zfhmin -verify-machineinstrs \
; RUN: < %s | FileCheck -check-prefix=RV64IZFHMIN %s
; RUN: llc -mtriple=riscv32 -mattr=+zhinxmin -verify-machineinstrs \
; RUN: llc -mtriple=riscv32 -target-abi ilp32 -mattr=+zhinxmin -verify-machineinstrs \
; RUN: < %s | FileCheck --check-prefixes=RVIZHINXMIN,RV32IZHINXMIN %s
; RUN: llc -mtriple=riscv64 -mattr=+zhinxmin -verify-machineinstrs \
; RUN: llc -mtriple=riscv64 -target-abi lp64 -mattr=+zhinxmin -verify-machineinstrs \
; RUN: < %s | FileCheck --check-prefixes=RVIZHINXMIN,RV64IZHINXMIN %s

; This file tests cases where simple floating point operations can be
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8 changes: 4 additions & 4 deletions llvm/test/CodeGen/RISCV/half-fcmp.ll
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Expand Up @@ -8,17 +8,17 @@
; RUN: llc -mtriple=riscv64 -mattr=+zhinx -verify-machineinstrs \
; RUN: -target-abi lp64 < %s | FileCheck -check-prefix=CHECKIZHINX %s
; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
; RUN: < %s | FileCheck -check-prefix=RV32I %s
; RUN: -target-abi ilp32 < %s | FileCheck -check-prefix=RV32I %s
; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
; RUN: < %s | FileCheck -check-prefix=RV64I %s
; RUN: -target-abi lp64 < %s | FileCheck -check-prefix=RV64I %s
; RUN: llc -mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs \
; RUN: -target-abi ilp32f < %s | FileCheck -check-prefix=CHECKIZFHMIN-ILP32F-LP64F %s
; RUN: llc -mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs \
; RUN: -target-abi lp64f < %s | FileCheck -check-prefix=CHECKIZFHMIN-ILP32F-LP64F %s
; RUN: llc -mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs \
; RUN: < %s | FileCheck -check-prefix=CHECKIZFHMIN %s
; RUN: -target-abi ilp32 < %s | FileCheck -check-prefix=CHECKIZFHMIN %s
; RUN: llc -mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs \
; RUN: < %s | FileCheck -check-prefix=CHECKIZFHMIN %s
; RUN: -target-abi lp64 < %s | FileCheck -check-prefix=CHECKIZFHMIN %s
; RUN: llc -mtriple=riscv32 -mattr=+zhinxmin -verify-machineinstrs \
; RUN: -target-abi ilp32 < %s | FileCheck -check-prefix=CHECKIZHINXMIN %s
; RUN: llc -mtriple=riscv64 -mattr=+zhinxmin -verify-machineinstrs \
Expand Down