Skip to content

[X86][MC] Keep backward compatibility in inline asm for constraints #73529

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 3 commits into from
Nov 28, 2023
Merged

[X86][MC] Keep backward compatibility in inline asm for constraints #73529

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
3 commits
Select commit Hold shift + click to select a range
99d8ae2
[X86][MC] Keep backward compatibility in inline asm for new registers
KanRobert Nov 27, 2023
737a1f5
Simplify the test
KanRobert Nov 28, 2023
d34dc11
Update test
KanRobert Nov 28, 2023
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
16 changes: 8 additions & 8 deletions llvm/lib/Target/X86/X86ISelLowering.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -56939,13 +56939,13 @@ X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
if (Subtarget.is64Bit()) {
if (VT == MVT::i8 || VT == MVT::i1)
return std::make_pair(0U, &X86::GR8RegClass);
return std::make_pair(0U, &X86::GR8_NOREX2RegClass);
if (VT == MVT::i16)
return std::make_pair(0U, &X86::GR16RegClass);
return std::make_pair(0U, &X86::GR16_NOREX2RegClass);
if (VT == MVT::i32 || VT == MVT::f32)
return std::make_pair(0U, &X86::GR32RegClass);
return std::make_pair(0U, &X86::GR32_NOREX2RegClass);
if (VT != MVT::f80 && !VT.isVector())
return std::make_pair(0U, &X86::GR64RegClass);
return std::make_pair(0U, &X86::GR64_NOREX2RegClass);
break;
}
[[fallthrough]];
Expand All @@ -56964,14 +56964,14 @@ X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
case 'r': // GENERAL_REGS
case 'l': // INDEX_REGS
if (VT == MVT::i8 || VT == MVT::i1)
return std::make_pair(0U, &X86::GR8RegClass);
return std::make_pair(0U, &X86::GR8_NOREX2RegClass);
if (VT == MVT::i16)
return std::make_pair(0U, &X86::GR16RegClass);
return std::make_pair(0U, &X86::GR16_NOREX2RegClass);
if (VT == MVT::i32 || VT == MVT::f32 ||
(!VT.isVector() && !Subtarget.is64Bit()))
return std::make_pair(0U, &X86::GR32RegClass);
return std::make_pair(0U, &X86::GR32_NOREX2RegClass);
if (VT != MVT::f80 && !VT.isVector())
return std::make_pair(0U, &X86::GR64RegClass);
return std::make_pair(0U, &X86::GR64_NOREX2RegClass);
break;
case 'R': // LEGACY_REGS
if (VT == MVT::i8 || VT == MVT::i1)
Expand Down
21 changes: 21 additions & 0 deletions llvm/test/CodeGen/X86/apx/asm-constraint.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,21 @@
; Check r16-r31 can not be used with 'q','r','l' constraint for backward compatibility.
; RUN: not llc < %s -mtriple=x86_64-unknown-unknown -mattr=+egpr 2>&1 | FileCheck %s

define void @q() {
; CHECK: error: inline assembly requires more registers than available
%a = call i32 asm sideeffect "movq %rax, $0", "=q,~{rax},~{rbx},~{rcx},~{rdx},~{rdi},~{rsi},~{rbp},~{rsp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
ret void
}

define void @r() {
; CHECK: error: inline assembly requires more registers than available
%a = call i32 asm sideeffect "movq %rax, $0", "=r,~{rax},~{rbx},~{rcx},~{rdx},~{rdi},~{rsi},~{rbp},~{rsp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
ret void
}

define void @l() {
; CHECK: error: inline assembly requires more registers than available
%a = call i32 asm sideeffect "movq %rax, $0", "=l,~{rax},~{rbx},~{rcx},~{rdx},~{rdi},~{rsi},~{rbp},~{rsp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
ret void
}

2 changes: 1 addition & 1 deletion llvm/test/CodeGen/X86/callbr-asm-bb-exports.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -16,7 +16,7 @@
; CHECK-NEXT: t2: i32,ch = CopyFromReg t0, Register:i32 %2
; CHECK-NEXT: t8: i32 = add t2, Constant:i32<4>
; CHECK-NEXT: t22: ch,glue = CopyToReg t17, Register:i32 %5, t8
; CHECK-NEXT: t29: ch,glue = inlineasm_br t22, TargetExternalSymbol:i64'xorl $0, $0; jmp ${1:l}', MDNode:ch<null>, TargetConstant:i64<0>, TargetConstant:i32<2359305>, Register:i32 %5, TargetConstant:i64<13>, BasicBlock:ch<fail 0x{{[0-9a-f]+}}>, TargetConstant:i32<12>, Register:i32 $df, TargetConstant:i32<12>, Register:i16 $fpsw, TargetConstant:i32<12>, Register:i32 $eflags, t22:1
; CHECK-NEXT: t29: ch,glue = inlineasm_br t22, TargetExternalSymbol:i64'xorl $0, $0; jmp ${1:l}', MDNode:ch<null>, TargetConstant:i64<0>, TargetConstant:i32<2686985>, Register:i32 %5, TargetConstant:i64<13>, BasicBlock:ch<fail 0x{{[0-9a-f]+}}>, TargetConstant:i32<12>, Register:i32 $df, TargetConstant:i32<12>, Register:i16 $fpsw, TargetConstant:i32<12>, Register:i32 $eflags, t22:1

define i32 @test(i32 %a, i32 %b, i32 %c) {
entry:
Expand Down
20 changes: 11 additions & 9 deletions llvm/test/CodeGen/X86/callbr-asm-outputs-indirect-isel-m32.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -10,11 +10,12 @@ define i8 @emulator_cmpxchg_emulated() {
; CHECK-NEXT: successors: %bb.1(0x80000000), %bb.2(0x00000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm $noreg, 1, $noreg, 0, $noreg :: (load (s32) from `ptr null`, align 8)
; CHECK-NEXT: INLINEASM_BR &"", 16 /* maystore attdialect */, 2359306 /* regdef:GR32 */, def %2, 2359306 /* regdef:GR32 */, def %3, 2147549193 /* reguse tiedto:$1 */, [[MOV32rm]](tied-def 5), 13 /* imm */, %bb.2
; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $eflags
; CHECK-NEXT: $eflags = COPY [[COPY]]
; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32_norex2 = COPY [[MOV32rm]]
; CHECK-NEXT: INLINEASM_BR &"", 16 /* maystore attdialect */, 2359306 /* regdef:GR32 */, def %2, 2686986 /* regdef:GR32_NOREX2 */, def %3, 2147549193 /* reguse tiedto:$1 */, [[COPY]](tied-def 5), 13 /* imm */, %bb.2
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $eflags
; CHECK-NEXT: $eflags = COPY [[COPY1]]
; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY %3
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr32 = COPY %3
; CHECK-NEXT: JMP_1 %bb.1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1.asm.fallthrough:
Expand Down Expand Up @@ -49,15 +50,16 @@ define i32 @emulator_cmpxchg_emulated2() {
; CHECK-NEXT: successors: %bb.1(0x80000000), %bb.2(0x00000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm $noreg, 1, $noreg, 0, $noreg :: (load (s32) from `ptr null`, align 8)
; CHECK-NEXT: INLINEASM_BR &"", 16 /* maystore attdialect */, 2359306 /* regdef:GR32 */, def %2, 2359306 /* regdef:GR32 */, def %3, 2147549193 /* reguse tiedto:$1 */, [[MOV32rm]](tied-def 5), 13 /* imm */, %bb.2
; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $eflags
; CHECK-NEXT: $eflags = COPY [[COPY]]
; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32_norex2 = COPY [[MOV32rm]]
; CHECK-NEXT: INLINEASM_BR &"", 16 /* maystore attdialect */, 2359306 /* regdef:GR32 */, def %2, 2686986 /* regdef:GR32_NOREX2 */, def %3, 2147549193 /* reguse tiedto:$1 */, [[COPY]](tied-def 5), 13 /* imm */, %bb.2
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $eflags
; CHECK-NEXT: $eflags = COPY [[COPY1]]
; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY %3
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr32 = COPY %3
; CHECK-NEXT: JMP_1 %bb.1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1.asm.fallthrough:
; CHECK-NEXT: $eax = COPY [[COPY1]]
; CHECK-NEXT: $eax = COPY [[COPY2]]
; CHECK-NEXT: RET 0, $eax
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.efaultu64.split (machine-block-address-taken, inlineasm-br-indirect-target):
Expand Down
16 changes: 8 additions & 8 deletions llvm/test/CodeGen/X86/callbr-asm-outputs-indirect-isel.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -10,7 +10,7 @@ define i32 @test0() {
; CHECK: bb.0 (%ir-block.0):
; CHECK-NEXT: successors: %bb.1(0x80000000), %bb.2(0x00000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: INLINEASM_BR &"", 0 /* attdialect */, 2359306 /* regdef:GR32 */, def %1, 13 /* imm */, %bb.2
; CHECK-NEXT: INLINEASM_BR &"", 0 /* attdialect */, 2686986 /* regdef:GR32_NOREX2 */, def %1, 13 /* imm */, %bb.2
; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY %1
; CHECK-NEXT: JMP_1 %bb.1
; CHECK-NEXT: {{ $}}
Expand Down Expand Up @@ -39,7 +39,7 @@ define i32 @test1() {
; CHECK-NEXT: successors: %bb.2(0x80000000), %bb.1(0x00000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[MOV32ri:%[0-9]+]]:gr32 = MOV32ri 42
; CHECK-NEXT: INLINEASM_BR &"", 0 /* attdialect */, 2359306 /* regdef:GR32 */, def %4, 13 /* imm */, %bb.1
; CHECK-NEXT: INLINEASM_BR &"", 0 /* attdialect */, 2686986 /* regdef:GR32_NOREX2 */, def %4, 13 /* imm */, %bb.1
; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY %4
; CHECK-NEXT: JMP_1 %bb.2
; CHECK-NEXT: {{ $}}
Expand Down Expand Up @@ -72,7 +72,7 @@ define i32 @test2() {
; CHECK-NEXT: successors: %bb.2(0x80000000), %bb.1(0x00000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[MOV32ri:%[0-9]+]]:gr32 = MOV32ri 42
; CHECK-NEXT: INLINEASM_BR &"", 0 /* attdialect */, 2359306 /* regdef:GR32 */, def %5, 2359306 /* regdef:GR32 */, def %6, 13 /* imm */, %bb.1
; CHECK-NEXT: INLINEASM_BR &"", 0 /* attdialect */, 2686986 /* regdef:GR32_NOREX2 */, def %5, 2686986 /* regdef:GR32_NOREX2 */, def %6, 13 /* imm */, %bb.1
; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY %6
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY %5
; CHECK-NEXT: JMP_1 %bb.2
Expand Down Expand Up @@ -232,15 +232,15 @@ define i64 @test6() {
; CHECK-NEXT: liveins: $rdx
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY4:%[0-9]+]]:gr64 = COPY $rdx
; CHECK-NEXT: %3:gr64 = COPY [[COPY4]]
; CHECK-NEXT: [[COPY5:%[0-9]+]]:gr64 = COPY [[COPY4]]
; CHECK-NEXT: JMP_1 %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.4.foo.split2 (machine-block-address-taken, inlineasm-br-indirect-target):
; CHECK-NEXT: successors: %bb.2(0x80000000)
; CHECK-NEXT: liveins: $rbx
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY6:%[0-9]+]]:gr64 = COPY $rbx
; CHECK-NEXT: %4:gr64 = COPY [[COPY6]]
; CHECK-NEXT: [[COPY7:%[0-9]+]]:gr64 = COPY [[COPY6]]
; CHECK-NEXT: JMP_1 %bb.2
entry:
%0 = callbr i64 asm "", "={dx},!i"()
Expand Down Expand Up @@ -291,7 +291,7 @@ define i32 @test7() {
; CHECK-NEXT: liveins: $edx
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY3:%[0-9]+]]:gr32 = COPY $edx
; CHECK-NEXT: %2:gr32 = COPY [[COPY3]]
; CHECK-NEXT: [[COPY4:%[0-9]+]]:gr32 = COPY [[COPY3]]
; CHECK-NEXT: JMP_1 %bb.1
entry:
br label %retry
Expand All @@ -317,8 +317,8 @@ define i32 @test8() {
; CHECK: bb.0.entry:
; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: INLINEASM_BR &"# $0", 0 /* attdialect */, 2359306 /* regdef:GR32 */, def %1, 13 /* imm */, %bb.1
; CHECK-NEXT: %0:gr32 = COPY %1
; CHECK-NEXT: INLINEASM_BR &"# $0", 0 /* attdialect */, 2686986 /* regdef:GR32_NOREX2 */, def %1, 13 /* imm */, %bb.1
; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY %1
; CHECK-NEXT: JMP_1 %bb.1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1.cleanup (machine-block-address-taken, inlineasm-br-indirect-target):
Expand Down