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[llvm][PowerPC] Correct handling of spill slots for SPE when EXPENSIVE_CHECKS is enabled #73940

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Merged
merged 2 commits into from
Dec 1, 2023
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[llvm][PowerPC] Correct handling of spill slots for SPE when EXPENSIVE_CHECKS is enabled #73940

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[llvm][PowerPC] Correct handling of spill slots for SPE when EXPENSIV…
DavidSpickett Nov 30, 2023
256ea80
MCPhysReg as copy.
DavidSpickett Dec 1, 2023
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24 changes: 8 additions & 16 deletions llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2334,24 +2334,16 @@ bool PPCFrameLowering::assignCalleeSavedSpillSlots(
// In case of SPE we only have SuperRegs and CRs
// in our CalleSaveInfo vector.

unsigned Idx = 0;
for (auto &CalleeSaveReg : CSI) {
const MCPhysReg &Reg = CalleeSaveReg.getReg();
const MCPhysReg &Lower = RegInfo->getSubReg(Reg, 1);
const MCPhysReg &Higher = RegInfo->getSubReg(Reg, 2);

// Check only for SuperRegs.
if (Lower) {
if (MRI.isPhysRegModified(Higher)) {
Idx++;
continue;
} else {
MCPhysReg Reg = CalleeSaveReg.getReg();
MCPhysReg Lower = RegInfo->getSubReg(Reg, 1);
MCPhysReg Higher = RegInfo->getSubReg(Reg, 2);

if ( // Check only for SuperRegs.
Lower &&
// Replace Reg if only lower-32 bits modified
CSI.erase(CSI.begin() + Idx);
CSI.insert(CSI.begin() + Idx, CalleeSavedInfo(Lower));
}
}
Idx++;
!MRI.isPhysRegModified(Higher))
CalleeSaveReg = CalleeSavedInfo(Lower);
}
}

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