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[RISCV] Remove unecessary early exit in transferBefore #74040

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Merged
merged 3 commits into from
Dec 12, 2023
Merged

[RISCV] Remove unecessary early exit in transferBefore #74040

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a60c334
[RISCV] Remove unecessary early exit in transferBefore
lukel97 Dec 1, 2023
079473d
Update test outside of rvv directory
lukel97 Dec 1, 2023
e7b4ea5
Rebase and update test
lukel97 Dec 12, 2023
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5 changes: 0 additions & 5 deletions llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1062,11 +1062,6 @@ void RISCVInsertVSETVLI::transferBefore(VSETVLIInfo &Info,
if (Info.hasSEWLMULRatioOnly() || !Info.isValid() || Info.isUnknown())
Info = NewInfo;

if (!RISCVII::hasVLOp(TSFlags)) {
Info = NewInfo;
return;
}

DemandedFields Demanded = getDemanded(MI, MRI, ST);
const VSETVLIInfo IncomingInfo =
adjustIncoming(PrevInfo, NewInfo, Demanded, MRI);
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/RISCV/65704-illegal-instruction.ll
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Expand Up @@ -22,11 +22,11 @@ define void @foo(<vscale x 8 x i8> %0) {
; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 0, e8, m1, tu, ma
; CHECK-NEXT: vslideup.vi v9, v10, 0
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma
; CHECK-NEXT: vmv.x.s s0, v9
; CHECK-NEXT: vsetivli zero, 0, e8, m1, tu, ma
; CHECK-NEXT: vsetvli zero, zero, e8, m1, tu, ma
; CHECK-NEXT: vslideup.vi v8, v9, 0
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma
; CHECK-NEXT: vmv.x.s s1, v8
; CHECK-NEXT: .LBB0_1: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: li a1, 0
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/RISCV/double_reduct.ll
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Expand Up @@ -113,7 +113,7 @@ define i16 @add_ext_v32i16(<32 x i8> %a, <16 x i8> %b) {
; CHECK-NEXT: li a0, 32
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
; CHECK-NEXT: vwredsumu.vs v8, v8, v10
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%ae = zext <32 x i8> %a to <32 x i16>
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20 changes: 10 additions & 10 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll
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Expand Up @@ -106,7 +106,7 @@ define i1 @extractelt_v16i1(ptr %x, i64 %idx) nounwind {
; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV32-NEXT: vle8.v v8, (a0)
; RV32-NEXT: vmseq.vi v8, v8, 0
; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; RV32-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: srl a0, a0, a1
; RV32-NEXT: andi a0, a0, 1
Expand All @@ -117,7 +117,7 @@ define i1 @extractelt_v16i1(ptr %x, i64 %idx) nounwind {
; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV64-NEXT: vle8.v v8, (a0)
; RV64-NEXT: vmseq.vi v8, v8, 0
; RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; RV64-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: srl a0, a0, a1
; RV64-NEXT: andi a0, a0, 1
Expand All @@ -128,7 +128,7 @@ define i1 @extractelt_v16i1(ptr %x, i64 %idx) nounwind {
; RV32ZBS-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV32ZBS-NEXT: vle8.v v8, (a0)
; RV32ZBS-NEXT: vmseq.vi v8, v8, 0
; RV32ZBS-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; RV32ZBS-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; RV32ZBS-NEXT: vmv.x.s a0, v8
; RV32ZBS-NEXT: bext a0, a0, a1
; RV32ZBS-NEXT: ret
Expand All @@ -138,7 +138,7 @@ define i1 @extractelt_v16i1(ptr %x, i64 %idx) nounwind {
; RV64ZBS-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV64ZBS-NEXT: vle8.v v8, (a0)
; RV64ZBS-NEXT: vmseq.vi v8, v8, 0
; RV64ZBS-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; RV64ZBS-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; RV64ZBS-NEXT: vmv.x.s a0, v8
; RV64ZBS-NEXT: bext a0, a0, a1
; RV64ZBS-NEXT: ret
Expand All @@ -155,7 +155,7 @@ define i1 @extractelt_v32i1(ptr %x, i64 %idx) nounwind {
; RV32-NEXT: vsetvli zero, a2, e8, m2, ta, ma
; RV32-NEXT: vle8.v v8, (a0)
; RV32-NEXT: vmseq.vi v10, v8, 0
; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; RV32-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; RV32-NEXT: vmv.x.s a0, v10
; RV32-NEXT: srl a0, a0, a1
; RV32-NEXT: andi a0, a0, 1
Expand All @@ -167,7 +167,7 @@ define i1 @extractelt_v32i1(ptr %x, i64 %idx) nounwind {
; RV64-NEXT: vsetvli zero, a2, e8, m2, ta, ma
; RV64-NEXT: vle8.v v8, (a0)
; RV64-NEXT: vmseq.vi v10, v8, 0
; RV64-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; RV64-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; RV64-NEXT: vmv.x.s a0, v10
; RV64-NEXT: srl a0, a0, a1
; RV64-NEXT: andi a0, a0, 1
Expand All @@ -179,7 +179,7 @@ define i1 @extractelt_v32i1(ptr %x, i64 %idx) nounwind {
; RV32ZBS-NEXT: vsetvli zero, a2, e8, m2, ta, ma
; RV32ZBS-NEXT: vle8.v v8, (a0)
; RV32ZBS-NEXT: vmseq.vi v10, v8, 0
; RV32ZBS-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; RV32ZBS-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; RV32ZBS-NEXT: vmv.x.s a0, v10
; RV32ZBS-NEXT: bext a0, a0, a1
; RV32ZBS-NEXT: ret
Expand All @@ -190,7 +190,7 @@ define i1 @extractelt_v32i1(ptr %x, i64 %idx) nounwind {
; RV64ZBS-NEXT: vsetvli zero, a2, e8, m2, ta, ma
; RV64ZBS-NEXT: vle8.v v8, (a0)
; RV64ZBS-NEXT: vmseq.vi v10, v8, 0
; RV64ZBS-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; RV64ZBS-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; RV64ZBS-NEXT: vmv.x.s a0, v10
; RV64ZBS-NEXT: bext a0, a0, a1
; RV64ZBS-NEXT: ret
Expand Down Expand Up @@ -221,7 +221,7 @@ define i1 @extractelt_v64i1(ptr %x, i64 %idx) nounwind {
; RV64-NEXT: vsetvli zero, a2, e8, m4, ta, ma
; RV64-NEXT: vle8.v v8, (a0)
; RV64-NEXT: vmseq.vi v12, v8, 0
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV64-NEXT: vsetvli zero, a2, e64, m1, ta, ma
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@lukel97 lukel97 Dec 1, 2023 •
edited
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We're preserving the AVL here but changing the VTYPE, i.e. performing the minimal change needed to get the correct state, which is what transferBefore should be doing. This looks like a case where the postpass could be replacing it with 1 to reduce the live range

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Another way to look at this is that transferBefore should chose to use the next AVL (1) since it has the choice here, and using the previous VL extends the live range. I'm fine with this landing as is, but this might be a good follow up.

; RV64-NEXT: vmv.x.s a0, v12
; RV64-NEXT: srl a0, a0, a1
; RV64-NEXT: andi a0, a0, 1
Expand All @@ -246,7 +246,7 @@ define i1 @extractelt_v64i1(ptr %x, i64 %idx) nounwind {
; RV64ZBS-NEXT: vsetvli zero, a2, e8, m4, ta, ma
; RV64ZBS-NEXT: vle8.v v8, (a0)
; RV64ZBS-NEXT: vmseq.vi v12, v8, 0
; RV64ZBS-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV64ZBS-NEXT: vsetvli zero, a2, e64, m1, ta, ma
; RV64ZBS-NEXT: vmv.x.s a0, v12
; RV64ZBS-NEXT: bext a0, a0, a1
; RV64ZBS-NEXT: ret
Expand Down
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