[ARM][FPEnv] Lowering of fpmode intrinsics #74054
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LLVM intrinsics `get_fpmode`, `set_fpmode` and `reset_fpmode` operate control modes, the bits of FP environment that affect FP operations. On ARM these bits are in FPSCR together with the status bits. The implementation of these intrinsics produces code close to that of functions `fegetmode` and `fesetmode` from GLIBC.
spavloff
requested review from
TNorthover,
john-brawn-arm and
david-greene-cb
|
@llvm/pr-subscribers-backend-arm Author: Serge Pavlov (spavloff) ChangesLLVM intrinsics Full diff: https://github.com/llvm/llvm-project/pull/74054.diff 4 Files Affected:
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index c8632d2aedb16ff..0acf6447fb878c6 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -1415,6 +1415,9 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::GET_FPENV, MVT::i32, Legal);
setOperationAction(ISD::SET_FPENV, MVT::i32, Legal);
setOperationAction(ISD::RESET_FPENV, MVT::Other, Legal);
+ setOperationAction(ISD::GET_FPMODE, MVT::i32, Legal);
+ setOperationAction(ISD::SET_FPMODE, MVT::i32, Custom);
+ setOperationAction(ISD::RESET_FPMODE, MVT::Other, Custom);
}
// We want to custom lower some of our intrinsics.
@@ -6447,6 +6450,57 @@ SDValue ARMTargetLowering::LowerSET_ROUNDING(SDValue Op,
return DAG.getNode(ISD::INTRINSIC_VOID, DL, MVT::Other, Ops2);
}
+SDValue ARMTargetLowering::LowerSET_FPMODE(SDValue Op,
+ SelectionDAG &DAG) const {
+ SDLoc DL(Op);
+ SDValue Chain = Op->getOperand(0);
+ SDValue Mode = Op->getOperand(1);
+
+ // Generate nodes to build:
+ // FPSCR = (FPSCR & FPStatusBits) | (Mode & ~FPStatusBits)
+ SDValue Ops[] = {Chain,
+ DAG.getConstant(Intrinsic::arm_get_fpscr, DL, MVT::i32)};
+ SDValue FPSCR =
+ DAG.getNode(ISD::INTRINSIC_W_CHAIN, DL, {MVT::i32, MVT::Other}, Ops);
+ Chain = FPSCR.getValue(1);
+ FPSCR = FPSCR.getValue(0);
+
+ SDValue FPSCRMasked =
+ DAG.getNode(ISD::AND, DL, MVT::i32, FPSCR,
+ DAG.getConstant(ARM::FPStatusBits, DL, MVT::i32));
+ SDValue InputMasked =
+ DAG.getNode(ISD::AND, DL, MVT::i32, Mode,
+ DAG.getConstant(~ARM::FPStatusBits, DL, MVT::i32));
+ FPSCR = DAG.getNode(ISD::OR, DL, MVT::i32, FPSCRMasked, InputMasked);
+
+ SDValue Ops2[] = {
+ Chain, DAG.getConstant(Intrinsic::arm_set_fpscr, DL, MVT::i32), FPSCR};
+ return DAG.getNode(ISD::INTRINSIC_VOID, DL, MVT::Other, Ops2);
+}
+
+SDValue ARMTargetLowering::LowerRESET_FPMODE(SDValue Op,
+ SelectionDAG &DAG) const {
+ SDLoc DL(Op);
+ SDValue Chain = Op->getOperand(0);
+
+ // To get the default FP mode all control bits are cleared:
+ // FPSCR = FPSCR & (FPStatusBits | FPReservedBits)
+ SDValue Ops[] = {Chain,
+ DAG.getConstant(Intrinsic::arm_get_fpscr, DL, MVT::i32)};
+ SDValue FPSCR =
+ DAG.getNode(ISD::INTRINSIC_W_CHAIN, DL, {MVT::i32, MVT::Other}, Ops);
+ Chain = FPSCR.getValue(1);
+ FPSCR = FPSCR.getValue(0);
+
+ SDValue FPSCRMasked = DAG.getNode(
+ ISD::AND, DL, MVT::i32, FPSCR,
+ DAG.getConstant(ARM::FPStatusBits | ARM::FPReservedBits, DL, MVT::i32));
+ SDValue Ops2[] = {Chain,
+ DAG.getConstant(Intrinsic::arm_set_fpscr, DL, MVT::i32),
+ FPSCRMasked};
+ return DAG.getNode(ISD::INTRINSIC_VOID, DL, MVT::Other, Ops2);
+}
+
static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG,
const ARMSubtarget *ST) {
SDLoc dl(N);
@@ -10560,6 +10614,8 @@ SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
case ISD::ZERO_EXTEND: return LowerVectorExtend(Op.getNode(), DAG, Subtarget);
case ISD::GET_ROUNDING: return LowerGET_ROUNDING(Op, DAG);
case ISD::SET_ROUNDING: return LowerSET_ROUNDING(Op, DAG);
+ case ISD::SET_FPMODE: return LowerSET_FPMODE(Op, DAG);
+ case ISD::RESET_FPMODE: return LowerRESET_FPMODE(Op, DAG);
case ISD::MUL: return LowerMUL(Op, DAG);
case ISD::SDIV:
if (Subtarget->isTargetWindows() && !Op.getValueType().isVector())
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.h b/llvm/lib/Target/ARM/ARMISelLowering.h
index 6c2b92de7a1df2f..84ba575a1467113 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.h
+++ b/llvm/lib/Target/ARM/ARMISelLowering.h
@@ -375,6 +375,14 @@ class VectorType;
// Bit position of rounding mode bits in FPSCR.
const unsigned RoundingBitsPos = 22;
+
+ // Bits of floating-point status. These are NZCV flags, QC bit and cumulative
+ // FP exception bits.
+ const unsigned FPStatusBits = 0xf800009f;
+
+ // Some bits in the FPSCR are not yet defined. They must be preserved when
+ // modifying the contents.
+ const unsigned FPReservedBits = 0x00086060;
} // namespace ARM
/// Define some predicates that are used for node matching.
@@ -835,6 +843,8 @@ class VectorType;
SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerGET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
+ SDValue LowerSET_FPMODE(SDValue Op, SelectionDAG &DAG) const;
+ SDValue LowerRESET_FPMODE(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerConstantFP(SDValue Op, SelectionDAG &DAG,
const ARMSubtarget *ST) const;
SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
diff --git a/llvm/lib/Target/ARM/ARMInstrVFP.td b/llvm/lib/Target/ARM/ARMInstrVFP.td
index 800527bcf756c6b..55d3efbd9b9a2b4 100644
--- a/llvm/lib/Target/ARM/ARMInstrVFP.td
+++ b/llvm/lib/Target/ARM/ARMInstrVFP.td
@@ -2675,6 +2675,7 @@ def : Pat<(get_fpenv), (VMRS)>;
def : Pat<(set_fpenv GPRnopc:$Rt), (VMSR GPRnopc:$Rt)>;
def : Pat<(reset_fpenv), (VMSR (MOVi 0))>, Requires<[IsARM]>;
def : Pat<(reset_fpenv), (VMSR (tMOVi8 0))>, Requires<[IsThumb]>;
+def : Pat<(get_fpmode), (VMRS)>;
//===----------------------------------------------------------------------===//
// Assembler aliases.
diff --git a/llvm/test/CodeGen/ARM/fpenv.ll b/llvm/test/CodeGen/ARM/fpenv.ll
index 40db627ebb3c239..fe0071926e48dd2 100644
--- a/llvm/test/CodeGen/ARM/fpenv.ll
+++ b/llvm/test/CodeGen/ARM/fpenv.ll
@@ -142,9 +142,107 @@ entry:
ret void
}
+define i32 @get_fpmode_01() #0 {
+; CHECK-LABEL: get_fpmode_01:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: .save {r11, lr}
+; CHECK-NEXT: push {r11, lr}
+; CHECK-NEXT: .pad #8
+; CHECK-NEXT: sub sp, sp, #8
+; CHECK-NEXT: add r0, sp, #4
+; CHECK-NEXT: bl fegetmode
+; CHECK-NEXT: ldr r0, [sp, #4]
+; CHECK-NEXT: add sp, sp, #8
+; CHECK-NEXT: pop {r11, lr}
+; CHECK-NEXT: mov pc, lr
+entry:
+ %fpenv = call i32 @llvm.get.fpmode.i32()
+ ret i32 %fpenv
+}
+
+define i32 @get_fpmode_02() nounwind {
+; CHECK-LABEL: get_fpmode_02:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vmrs r0, fpscr
+; CHECK-NEXT: mov pc, lr
+entry:
+ %fpenv = call i32 @llvm.get.fpmode.i32()
+ ret i32 %fpenv
+}
+
+define void @set_fpmode_01(i32 %fpmode) #0 {
+; CHECK-LABEL: set_fpmode_01:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: .save {r11, lr}
+; CHECK-NEXT: push {r11, lr}
+; CHECK-NEXT: .pad #8
+; CHECK-NEXT: sub sp, sp, #8
+; CHECK-NEXT: str r0, [sp, #4]
+; CHECK-NEXT: add r0, sp, #4
+; CHECK-NEXT: bl fesetmode
+; CHECK-NEXT: add sp, sp, #8
+; CHECK-NEXT: pop {r11, lr}
+; CHECK-NEXT: mov pc, lr
+entry:
+ call void @llvm.set.fpmode.i32(i32 %fpmode)
+ ret void
+}
+
+define void @set_fpmode_02(i32 %fpmode) nounwind {
+; CHECK-LABEL: set_fpmode_02:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vmrs r1, fpscr
+; CHECK-NEXT: mvn r2, #159
+; CHECK-NEXT: sub r2, r2, #-134217728
+; CHECK-NEXT: and r0, r0, r2
+; CHECK-NEXT: mov r2, #159
+; CHECK-NEXT: orr r2, r2, #-134217728
+; CHECK-NEXT: and r1, r1, r2
+; CHECK-NEXT: orr r0, r1, r0
+; CHECK-NEXT: vmsr fpscr, r0
+; CHECK-NEXT: mov pc, lr
+entry:
+ call void @llvm.set.fpmode.i32(i32 %fpmode)
+ ret void
+}
+
+define void @reset_fpmode_01() #0 {
+; CHECK-LABEL: reset_fpmode_01:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: .save {r11, lr}
+; CHECK-NEXT: push {r11, lr}
+; CHECK-NEXT: mvn r0, #0
+; CHECK-NEXT: bl fesetmode
+; CHECK-NEXT: pop {r11, lr}
+; CHECK-NEXT: mov pc, lr
+entry:
+ call void @llvm.reset.fpmode()
+ ret void
+}
+
+define void @reset_fpmode_02() nounwind {
+; CHECK-LABEL: reset_fpmode_02:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vmrs r0, fpscr
+; CHECK-NEXT: ldr r1, .LCPI16_0
+; CHECK-NEXT: and r0, r0, r1
+; CHECK-NEXT: vmsr fpscr, r0
+; CHECK-NEXT: mov pc, lr
+; CHECK-NEXT: .p2align 2
+; CHECK-NEXT: @ %bb.1:
+; CHECK-NEXT: .LCPI16_0:
+; CHECK-NEXT: .long 4161298687 @ 0xf80860ff
+entry:
+ call void @llvm.reset.fpmode()
+ ret void
+}
+
attributes #0 = { nounwind "use-soft-float"="true" }
declare void @llvm.set.rounding(i32)
declare i32 @llvm.get.fpenv.i32()
declare void @llvm.set.fpenv.i32(i32 %fpenv)
declare void @llvm.reset.fpenv()
+declare i32 @llvm.get.fpmode.i32()
+declare void @llvm.set.fpmode.i32(i32 %fpmode)
+declare void @llvm.reset.fpmode()
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||
| // Some bits in the FPSCR are not yet defined. They must be preserved when | ||
| // modifying the contents. | ||
| const unsigned FPReservedBits = 0x00086060; |
There was a problem hiding this comment.
This matches the value in https://sourceware.org/git/?p=glibc.git;a=blob;f=sysdeps/arm/fpu_control.h;h=cadbe927b3df20d06f6f4cf159c94e865a595885;hb=HEAD#l46, but I don't think it's right. Bit 0x80000 is the FZ16 bit, which is the same as the FZ bit but applies to fp16 values, so I think it should be considered a control bit, i.e. the value here should be 0x00006060.
There was a problem hiding this comment.
You are right, thank you!
qihangkong
pushed a commit
to rvgpu/rvgpu-llvm
that referenced
this pull request
Apr 23, 2024
LLVM intrinsics `get_fpmode`, `set_fpmode` and `reset_fpmode` operate control modes, the bits of FP environment that affect FP operations. On ARM these bits are in FPSCR together with the status bits. The implementation of these intrinsics produces code close to that of functions `fegetmode` and `fesetmode` from GLIBC. Pull request: llvm/llvm-project#74054
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LLVM intrinsics
get_fpmode,set_fpmodeandreset_fpmodeoperate control modes, the bits of FP environment that affect FP operations. On ARM these bits are in FPSCR together with the status bits. The implementation of these intrinsics produces code close to that of functionsfegetmodeandfesetmodefrom GLIBC.