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Merged
merged 1 commit into from
Dec 7, 2023
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Implement SoftPromoteHalf for FFREXP. #74076

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20 changes: 20 additions & 0 deletions llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2774,6 +2774,8 @@ void DAGTypeLegalizer::SoftPromoteHalfResult(SDNode *N, unsigned ResNo) {
case ISD::FPOWI:
case ISD::FLDEXP: R = SoftPromoteHalfRes_ExpOp(N); break;

case ISD::FFREXP: R = SoftPromoteHalfRes_FFREXP(N); break;

case ISD::LOAD: R = SoftPromoteHalfRes_LOAD(N); break;
case ISD::SELECT: R = SoftPromoteHalfRes_SELECT(N); break;
case ISD::SELECT_CC: R = SoftPromoteHalfRes_SELECT_CC(N); break;
Expand Down Expand Up @@ -2902,6 +2904,24 @@ SDValue DAGTypeLegalizer::SoftPromoteHalfRes_ExpOp(SDNode *N) {
return DAG.getNode(GetPromotionOpcode(NVT, OVT), dl, MVT::i16, Res);
}

SDValue DAGTypeLegalizer::SoftPromoteHalfRes_FFREXP(SDNode *N) {
EVT OVT = N->getValueType(0);
EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), OVT);
SDValue Op = GetSoftPromotedHalf(N->getOperand(0));
SDLoc dl(N);

// Promote to the larger FP type.
Op = DAG.getNode(GetPromotionOpcode(OVT, NVT), dl, NVT, Op);

SDValue Res = DAG.getNode(N->getOpcode(), dl,
DAG.getVTList(NVT, N->getValueType(1)), Op);

ReplaceValueWith(SDValue(N, 1), Res.getValue(1));

// Convert back to FP16 as an integer.
return DAG.getNode(GetPromotionOpcode(NVT, OVT), dl, MVT::i16, Res);
}

SDValue DAGTypeLegalizer::SoftPromoteHalfRes_FP_ROUND(SDNode *N) {
EVT RVT = N->getValueType(0);
EVT SVT = N->getOperand(0).getValueType();
Expand Down
1 change: 1 addition & 0 deletions llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
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Expand Up @@ -738,6 +738,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
SDValue SoftPromoteHalfRes_FCOPYSIGN(SDNode *N);
SDValue SoftPromoteHalfRes_FMAD(SDNode *N);
SDValue SoftPromoteHalfRes_ExpOp(SDNode *N);
SDValue SoftPromoteHalfRes_FFREXP(SDNode *N);
SDValue SoftPromoteHalfRes_FP_ROUND(SDNode *N);
SDValue SoftPromoteHalfRes_LOAD(SDNode *N);
SDValue SoftPromoteHalfRes_SELECT(SDNode *N);
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285 changes: 270 additions & 15 deletions llvm/test/CodeGen/RISCV/llvm.frexp.ll
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Expand Up @@ -18,24 +18,279 @@

; TODO: FIXMEs are copied blindly across from the X86 version of this test.

; FIXME
; define { half, i32 } @test_frexp_f16_i32(half %a) nounwind {
; %result = call { half, i32 } @llvm.frexp.f16.i32(half %a)
; ret { half, i32 } %result
; }
define { half, i32 } @test_frexp_f16_i32(half %a) nounwind {
; RV32IFD-LABEL: test_frexp_f16_i32:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: call __extendhfsf2@plt
; RV32IFD-NEXT: addi a0, sp, 8
; RV32IFD-NEXT: call frexpf@plt
; RV32IFD-NEXT: call __truncsfhf2@plt
; RV32IFD-NEXT: fmv.x.w a1, fa0
; RV32IFD-NEXT: lw a0, 8(sp)
; RV32IFD-NEXT: lui a2, 1048560
; RV32IFD-NEXT: or a1, a1, a2
; RV32IFD-NEXT: fmv.w.x fa0, a1
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: test_frexp_f16_i32:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: call __extendhfsf2@plt
; RV64IFD-NEXT: mv a0, sp
; RV64IFD-NEXT: call frexpf@plt
; RV64IFD-NEXT: call __truncsfhf2@plt
; RV64IFD-NEXT: fmv.x.w a1, fa0
; RV64IFD-NEXT: ld a0, 0(sp)
; RV64IFD-NEXT: lui a2, 1048560
; RV64IFD-NEXT: or a1, a1, a2
; RV64IFD-NEXT: fmv.w.x fa0, a1
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret
;
; RV32IZFINXZDINX-LABEL: test_frexp_f16_i32:
; RV32IZFINXZDINX: # %bb.0:
; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: call __extendhfsf2@plt
; RV32IZFINXZDINX-NEXT: addi a1, sp, 8
; RV32IZFINXZDINX-NEXT: call frexpf@plt
; RV32IZFINXZDINX-NEXT: call __truncsfhf2@plt
; RV32IZFINXZDINX-NEXT: lw a1, 8(sp)
; RV32IZFINXZDINX-NEXT: lui a2, 1048560
; RV32IZFINXZDINX-NEXT: or a0, a0, a2
; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: test_frexp_f16_i32:
; RV64IZFINXZDINX: # %bb.0:
; RV64IZFINXZDINX-NEXT: addi sp, sp, -16
; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IZFINXZDINX-NEXT: call __extendhfsf2@plt
; RV64IZFINXZDINX-NEXT: mv a1, sp
; RV64IZFINXZDINX-NEXT: call frexpf@plt
; RV64IZFINXZDINX-NEXT: call __truncsfhf2@plt
; RV64IZFINXZDINX-NEXT: ld a1, 0(sp)
; RV64IZFINXZDINX-NEXT: lui a2, 1048560
; RV64IZFINXZDINX-NEXT: or a0, a0, a2
; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IZFINXZDINX-NEXT: addi sp, sp, 16
; RV64IZFINXZDINX-NEXT: ret
;
; RV32I-LABEL: test_frexp_f16_i32:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a0, a0, 16
; RV32I-NEXT: srli a0, a0, 16
; RV32I-NEXT: call __extendhfsf2@plt
; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: call frexpf@plt
; RV32I-NEXT: call __truncsfhf2@plt
; RV32I-NEXT: lw a1, 8(sp)
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV64I-LABEL: test_frexp_f16_i32:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: slli a0, a0, 48
; RV64I-NEXT: srli a0, a0, 48
; RV64I-NEXT: call __extendhfsf2@plt
; RV64I-NEXT: addi a1, sp, 4
; RV64I-NEXT: call frexpf@plt
; RV64I-NEXT: call __truncsfhf2@plt
; RV64I-NEXT: lw a1, 4(sp)
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
%result = call { half, i32 } @llvm.frexp.f16.i32(half %a)
ret { half, i32 } %result
}

; define half @test_frexp_f16_i32_only_use_fract(half %a) nounwind {
; %result = call { half, i32 } @llvm.frexp.f16.i32(half %a)
; %result.0 = extractvalue { half, i32 } %result, 0
; ret half %result.0
; }
define half @test_frexp_f16_i32_only_use_fract(half %a) nounwind {
; RV32IFD-LABEL: test_frexp_f16_i32_only_use_fract:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: call __extendhfsf2@plt
; RV32IFD-NEXT: addi a0, sp, 8
; RV32IFD-NEXT: call frexpf@plt
; RV32IFD-NEXT: call __truncsfhf2@plt
; RV32IFD-NEXT: fmv.x.w a0, fa0
; RV32IFD-NEXT: lui a1, 1048560
; RV32IFD-NEXT: or a0, a0, a1
; RV32IFD-NEXT: fmv.w.x fa0, a0
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: test_frexp_f16_i32_only_use_fract:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: call __extendhfsf2@plt
; RV64IFD-NEXT: mv a0, sp
; RV64IFD-NEXT: call frexpf@plt
; RV64IFD-NEXT: call __truncsfhf2@plt
; RV64IFD-NEXT: fmv.x.w a0, fa0
; RV64IFD-NEXT: lui a1, 1048560
; RV64IFD-NEXT: or a0, a0, a1
; RV64IFD-NEXT: fmv.w.x fa0, a0
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret
;
; RV32IZFINXZDINX-LABEL: test_frexp_f16_i32_only_use_fract:
; RV32IZFINXZDINX: # %bb.0:
; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: call __extendhfsf2@plt
; RV32IZFINXZDINX-NEXT: addi a1, sp, 8
; RV32IZFINXZDINX-NEXT: call frexpf@plt
; RV32IZFINXZDINX-NEXT: call __truncsfhf2@plt
; RV32IZFINXZDINX-NEXT: lui a1, 1048560
; RV32IZFINXZDINX-NEXT: or a0, a0, a1
; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: test_frexp_f16_i32_only_use_fract:
; RV64IZFINXZDINX: # %bb.0:
; RV64IZFINXZDINX-NEXT: addi sp, sp, -16
; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IZFINXZDINX-NEXT: call __extendhfsf2@plt
; RV64IZFINXZDINX-NEXT: mv a1, sp
; RV64IZFINXZDINX-NEXT: call frexpf@plt
; RV64IZFINXZDINX-NEXT: call __truncsfhf2@plt
; RV64IZFINXZDINX-NEXT: lui a1, 1048560
; RV64IZFINXZDINX-NEXT: or a0, a0, a1
; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IZFINXZDINX-NEXT: addi sp, sp, 16
; RV64IZFINXZDINX-NEXT: ret
;
; RV32I-LABEL: test_frexp_f16_i32_only_use_fract:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a0, a0, 16
; RV32I-NEXT: srli a0, a0, 16
; RV32I-NEXT: call __extendhfsf2@plt
; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: call frexpf@plt
; RV32I-NEXT: call __truncsfhf2@plt
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV64I-LABEL: test_frexp_f16_i32_only_use_fract:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: slli a0, a0, 48
; RV64I-NEXT: srli a0, a0, 48
; RV64I-NEXT: call __extendhfsf2@plt
; RV64I-NEXT: addi a1, sp, 4
; RV64I-NEXT: call frexpf@plt
; RV64I-NEXT: call __truncsfhf2@plt
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
%result = call { half, i32 } @llvm.frexp.f16.i32(half %a)
%result.0 = extractvalue { half, i32 } %result, 0
ret half %result.0
}

; define i32 @test_frexp_f16_i32_only_use_exp(half %a) nounwind {
; %result = call { half, i32 } @llvm.frexp.f16.i32(half %a)
; %result.0 = extractvalue { half, i32 } %result, 1
; ret i32 %result.0
; }
define i32 @test_frexp_f16_i32_only_use_exp(half %a) nounwind {
; RV32IFD-LABEL: test_frexp_f16_i32_only_use_exp:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: call __extendhfsf2@plt
; RV32IFD-NEXT: addi a0, sp, 8
; RV32IFD-NEXT: call frexpf@plt
; RV32IFD-NEXT: lw a0, 8(sp)
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: test_frexp_f16_i32_only_use_exp:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: call __extendhfsf2@plt
; RV64IFD-NEXT: mv a0, sp
; RV64IFD-NEXT: call frexpf@plt
; RV64IFD-NEXT: ld a0, 0(sp)
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret
;
; RV32IZFINXZDINX-LABEL: test_frexp_f16_i32_only_use_exp:
; RV32IZFINXZDINX: # %bb.0:
; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: call __extendhfsf2@plt
; RV32IZFINXZDINX-NEXT: addi a1, sp, 8
; RV32IZFINXZDINX-NEXT: call frexpf@plt
; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: test_frexp_f16_i32_only_use_exp:
; RV64IZFINXZDINX: # %bb.0:
; RV64IZFINXZDINX-NEXT: addi sp, sp, -16
; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IZFINXZDINX-NEXT: call __extendhfsf2@plt
; RV64IZFINXZDINX-NEXT: mv a1, sp
; RV64IZFINXZDINX-NEXT: call frexpf@plt
; RV64IZFINXZDINX-NEXT: ld a0, 0(sp)
; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IZFINXZDINX-NEXT: addi sp, sp, 16
; RV64IZFINXZDINX-NEXT: ret
;
; RV32I-LABEL: test_frexp_f16_i32_only_use_exp:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a0, a0, 16
; RV32I-NEXT: srli a0, a0, 16
; RV32I-NEXT: call __extendhfsf2@plt
; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: call frexpf@plt
; RV32I-NEXT: lw a0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV64I-LABEL: test_frexp_f16_i32_only_use_exp:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: slli a0, a0, 48
; RV64I-NEXT: srli a0, a0, 48
; RV64I-NEXT: call __extendhfsf2@plt
; RV64I-NEXT: addi a1, sp, 4
; RV64I-NEXT: call frexpf@plt
; RV64I-NEXT: lw a0, 4(sp)
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
%result = call { half, i32 } @llvm.frexp.f16.i32(half %a)
%result.0 = extractvalue { half, i32 } %result, 1
ret i32 %result.0
}

; FIXME
; define { <2 x half>, <2 x i32> } @test_frexp_v2f16_v2i32(<2 x half> %a) nounwind {
; %result = call { <2 x half>, <2 x i32> } @llvm.frexp.v2f16.v2i32(<2 x half> %a)
; ret { <2 x half>, <2 x i32> } %result
Expand Down
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