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[AMDGPU] Add GFX12 encoding for VINTERP instructions #74616

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Merged
merged 4 commits into from
Dec 7, 2023
Merged

[AMDGPU] Add GFX12 encoding for VINTERP instructions #74616

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69580e5
[AMDGPU] Add GFX12 encoding for VINTERP instructions
jayfoad Feb 7, 2023
4939699
Add assembler error tests
jayfoad Dec 6, 2023
ee561b9
Merge remote-tracking branch 'origin/main' into gfx12-vinterp
jayfoad Dec 6, 2023
0968f1c
Merge remote-tracking branch 'origin/main' into gfx12-vinterp
jayfoad Dec 7, 2023
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6 changes: 5 additions & 1 deletion llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -782,9 +782,13 @@ DecodeStatus AMDGPUDisassembler::convertEXPInst(MCInst &MI) const {

DecodeStatus AMDGPUDisassembler::convertVINTERPInst(MCInst &MI) const {
if (MI.getOpcode() == AMDGPU::V_INTERP_P10_F16_F32_inreg_gfx11 ||
MI.getOpcode() == AMDGPU::V_INTERP_P10_F16_F32_inreg_gfx12 ||
MI.getOpcode() == AMDGPU::V_INTERP_P10_RTZ_F16_F32_inreg_gfx11 ||
MI.getOpcode() == AMDGPU::V_INTERP_P10_RTZ_F16_F32_inreg_gfx12 ||
MI.getOpcode() == AMDGPU::V_INTERP_P2_F16_F32_inreg_gfx11 ||
MI.getOpcode() == AMDGPU::V_INTERP_P2_RTZ_F16_F32_inreg_gfx11) {
MI.getOpcode() == AMDGPU::V_INTERP_P2_F16_F32_inreg_gfx12 ||
MI.getOpcode() == AMDGPU::V_INTERP_P2_RTZ_F16_F32_inreg_gfx11 ||
MI.getOpcode() == AMDGPU::V_INTERP_P2_RTZ_F16_F32_inreg_gfx12) {
// The MCInst has this field that is not directly encoded in the
// instruction.
insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::op_sel);
Expand Down
38 changes: 28 additions & 10 deletions llvm/lib/Target/AMDGPU/VINTERPInstructions.td
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Original file line number Diff line number Diff line change
Expand Up @@ -10,7 +10,7 @@
// VINTERP encoding
//===----------------------------------------------------------------------===//

class VINTERPe_gfx11 <bits<7> op, VOPProfile P> : Enc64 {
class VINTERPe <VOPProfile P> : Enc64 {
bits<8> vdst;
bits<4> src0_modifiers;
bits<9> src0;
Expand All @@ -31,7 +31,6 @@ class VINTERPe_gfx11 <bits<7> op, VOPProfile P> : Enc64 {
let Inst{13} = !if(P.HasOpSel, src2_modifiers{2}, 0); // op_sel(2)
let Inst{14} = !if(P.HasOpSel, src0_modifiers{3}, 0); // op_sel(3)
let Inst{15} = clamp;
let Inst{22-16} = op;
let Inst{40-32} = src0;
let Inst{49-41} = src1;
let Inst{58-50} = src2;
Expand All @@ -40,6 +39,14 @@ class VINTERPe_gfx11 <bits<7> op, VOPProfile P> : Enc64 {
let Inst{63} = src2_modifiers{0}; // neg(2)
}

class VINTERPe_gfx11 <bits<7> op, VOPProfile P> : VINTERPe<P> {
let Inst{22-16} = op;
}

class VINTERPe_gfx12 <bits<7> op, VOPProfile P> : VINTERPe<P> {
let Inst{20-16} = op{4-0};
}

//===----------------------------------------------------------------------===//
// VOP3 VINTERP
//===----------------------------------------------------------------------===//
Expand Down Expand Up @@ -171,17 +178,28 @@ defm : VInterpF16Pat<int_amdgcn_interp_inreg_p2_f16,
// VINTERP Real Instructions
//===----------------------------------------------------------------------===//

let AssemblerPredicate = isGFX11Plus, DecoderNamespace = "GFX11" in {
multiclass VINTERP_Real_gfx11 <bits<7> op> {
multiclass VINTERP_Real_gfx11 <bits<7> op> {
let AssemblerPredicate = isGFX11Only, DecoderNamespace = "GFX11" in {
def _gfx11 :
VINTERP_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.GFX11>,
VINTERPe_gfx11<op, !cast<VOP3_Pseudo>(NAME).Pfl>;
}
}

defm V_INTERP_P10_F32_inreg : VINTERP_Real_gfx11<0x000>;
defm V_INTERP_P2_F32_inreg : VINTERP_Real_gfx11<0x001>;
defm V_INTERP_P10_F16_F32_inreg : VINTERP_Real_gfx11<0x002>;
defm V_INTERP_P2_F16_F32_inreg : VINTERP_Real_gfx11<0x003>;
defm V_INTERP_P10_RTZ_F16_F32_inreg : VINTERP_Real_gfx11<0x004>;
defm V_INTERP_P2_RTZ_F16_F32_inreg : VINTERP_Real_gfx11<0x005>;
multiclass VINTERP_Real_gfx12 <bits<7> op> {
let AssemblerPredicate = isGFX12Only, DecoderNamespace = "GFX12" in {
def _gfx12 :
VINTERP_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.GFX12>,
VINTERPe_gfx12<op, !cast<VOP3_Pseudo>(NAME).Pfl>;
}
}

multiclass VINTERP_Real_gfx11_gfx12 <bits<7> op> :
VINTERP_Real_gfx11<op>, VINTERP_Real_gfx12<op>;

defm V_INTERP_P10_F32_inreg : VINTERP_Real_gfx11_gfx12<0x000>;
defm V_INTERP_P2_F32_inreg : VINTERP_Real_gfx11_gfx12<0x001>;
defm V_INTERP_P10_F16_F32_inreg : VINTERP_Real_gfx11_gfx12<0x002>;
defm V_INTERP_P2_F16_F32_inreg : VINTERP_Real_gfx11_gfx12<0x003>;
defm V_INTERP_P10_RTZ_F16_F32_inreg : VINTERP_Real_gfx11_gfx12<0x004>;
defm V_INTERP_P2_RTZ_F16_F32_inreg : VINTERP_Real_gfx11_gfx12<0x005>;
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