[X86] Allow constant pool references under medium code model in X86InstrInfo::foldMemoryOperandImpl()

[aeubanks]

The medium code model assumes that the constant pool is referenceable with 32-bit relocations.

[llvmbot]

@llvm/pr-subscribers-backend-x86

Author: Arthur Eubanks (aeubanks)

Changes

The medium code model assumes that the constant pool is referenceable with 32-bit relocations.

---

Full diff: https://github.com/llvm/llvm-project/pull/75011.diff

2 Files Affected:

• (modified) llvm/lib/Target/X86/X86InstrInfo.cpp (+2-3)
• (modified) llvm/test/CodeGen/X86/mmx-fold-zero.ll (+38-1)

diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp
index d6ae4971d238d..7b607c6f198c7 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.cpp
+++ b/llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -8026,9 +8026,8 @@ MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
     // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
     // Create a constant-pool entry and operands to load from it.
 
-    // Medium and large mode can't fold loads this way.
-    if (MF.getTarget().getCodeModel() != CodeModel::Small &&
-        MF.getTarget().getCodeModel() != CodeModel::Kernel)
+    // Large code model can't fold loads this way.
+    if (MF.getTarget().getCodeModel() == CodeModel::Large)
       return nullptr;
 
     // x86-32 PIC requires a PIC base register for constant pools.
diff --git a/llvm/test/CodeGen/X86/mmx-fold-zero.ll b/llvm/test/CodeGen/X86/mmx-fold-zero.ll
index d40146453cff0..b2c94e3aaa3a6 100644
--- a/llvm/test/CodeGen/X86/mmx-fold-zero.ll
+++ b/llvm/test/CodeGen/X86/mmx-fold-zero.ll
@@ -1,6 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+mmx,+sse2 | FileCheck %s --check-prefix=X86
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+mmx,+sse2 | FileCheck %s --check-prefix=X64
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+mmx,+sse2 -code-model=small | FileCheck %s --check-prefix=X64
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+mmx,+sse2 -code-model=medium | FileCheck %s --check-prefix=X64
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+mmx,+sse2 -code-model=large | FileCheck %s --check-prefix=X64-LARGE
 
 define double @mmx_zero(double, double, double, double) nounwind {
 ; X86-LABEL: mmx_zero:
@@ -78,6 +80,41 @@ define double @mmx_zero(double, double, double, double) nounwind {
 ; X64-NEXT:    paddw %mm2, %mm0
 ; X64-NEXT:    movq2dq %mm0, %xmm0
 ; X64-NEXT:    retq
+;
+; X64-LARGE-LABEL: mmx_zero:
+; X64-LARGE:       # %bb.0:
+; X64-LARGE-NEXT:    movdq2q %xmm0, %mm0
+; X64-LARGE-NEXT:    movdq2q %xmm1, %mm5
+; X64-LARGE-NEXT:    movq %mm5, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
+; X64-LARGE-NEXT:    movq %mm0, %mm3
+; X64-LARGE-NEXT:    paddd %mm5, %mm3
+; X64-LARGE-NEXT:    pxor %mm1, %mm1
+; X64-LARGE-NEXT:    movq %mm3, %mm6
+; X64-LARGE-NEXT:    pmuludq %mm1, %mm6
+; X64-LARGE-NEXT:    movdq2q %xmm2, %mm4
+; X64-LARGE-NEXT:    movq %mm6, %mm2
+; X64-LARGE-NEXT:    paddd %mm4, %mm2
+; X64-LARGE-NEXT:    paddw %mm2, %mm0
+; X64-LARGE-NEXT:    movq %mm5, %mm1
+; X64-LARGE-NEXT:    paddw %mm0, %mm1
+; X64-LARGE-NEXT:    movdq2q %xmm3, %mm5
+; X64-LARGE-NEXT:    movq %mm1, %mm7
+; X64-LARGE-NEXT:    pmuludq %mm5, %mm7
+; X64-LARGE-NEXT:    paddw %mm4, %mm7
+; X64-LARGE-NEXT:    paddw %mm7, %mm5
+; X64-LARGE-NEXT:    paddw %mm5, %mm2
+; X64-LARGE-NEXT:    paddw %mm2, %mm0
+; X64-LARGE-NEXT:    paddw %mm6, %mm0
+; X64-LARGE-NEXT:    pmuludq %mm3, %mm0
+; X64-LARGE-NEXT:    pxor %mm3, %mm3
+; X64-LARGE-NEXT:    paddw %mm3, %mm0
+; X64-LARGE-NEXT:    paddw %mm1, %mm0
+; X64-LARGE-NEXT:    pmuludq %mm7, %mm0
+; X64-LARGE-NEXT:    pmuludq {{[-0-9]+}}(%r{{[sb]}}p), %mm0 # 8-byte Folded Reload
+; X64-LARGE-NEXT:    paddw %mm5, %mm0
+; X64-LARGE-NEXT:    paddw %mm2, %mm0
+; X64-LARGE-NEXT:    movq2dq %mm0, %xmm0
+; X64-LARGE-NEXT:    retq
   %5 = bitcast double %0 to x86_mmx
   %6 = bitcast double %1 to x86_mmx
   %7 = tail call x86_mmx @llvm.x86.mmx.padd.d(x86_mmx %5, x86_mmx %6)