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[flang] update ppc-vec-store-elem-order.f90 after #74709 (NFC) #75064

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Merged
merged 1 commit into from
Dec 11, 2023
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[flang] update ppc-vec-store-elem-order.f90 after #74709 (NFC) #75064

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16 changes: 8 additions & 8 deletions flang/test/Lower/PowerPC/ppc-vec-store-elem-order.f90
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Original file line number Diff line number Diff line change
Expand Up @@ -67,10 +67,10 @@ subroutine vec_xstd2_test(arg1, arg2, arg3, i)

! LLVMIR: %[[i:.*]] = load i32, ptr %3, align 4
! LLVMIR: %[[iext:.*]] = sext i32 %[[i]] to i64
! LLVMIR: %[[isub:.*]] = sub i64 %[[iext]], 1
! LLVMIR: %[[imul1:.*]] = mul i64 %[[isub]], 1
! LLVMIR: %[[imul2:.*]] = mul i64 %[[imul1]], 1
! LLVMIR: %[[iadd:.*]] = add i64 %[[imul2]], 0
! LLVMIR: %[[isub:.*]] = sub nsw i64 %[[iext]], 1
! LLVMIR: %[[imul1:.*]] = mul nsw i64 %[[isub]], 1
! LLVMIR: %[[imul2:.*]] = mul nsw i64 %[[imul1]], 1
! LLVMIR: %[[iadd:.*]] = add nsw i64 %[[imul2]], 0
! LLVMIR: %[[gep1:.*]] = getelementptr <4 x float>, ptr %2, i64 %[[iadd]]
! LLVMIR: %[[arg1:.*]] = load <4 x float>, ptr %0, align 16
! LLVMIR: %[[arg2:.*]] = load i16, ptr %1, align 2
Expand All @@ -93,10 +93,10 @@ subroutine vec_xstw4_test(arg1, arg2, arg3, i)

! LLVMIR: %[[i:.*]] = load i32, ptr %3, align 4
! LLVMIR: %[[iext:.*]] = sext i32 %[[i]] to i64
! LLVMIR: %[[isub:.*]] = sub i64 %[[iext]], 1
! LLVMIR: %[[imul1:.*]] = mul i64 %[[isub]], 1
! LLVMIR: %[[imul2:.*]] = mul i64 %[[imul1]], 1
! LLVMIR: %[[iadd:.*]] = add i64 %[[imul2]], 0
! LLVMIR: %[[isub:.*]] = sub nsw i64 %[[iext]], 1
! LLVMIR: %[[imul1:.*]] = mul nsw i64 %[[isub]], 1
! LLVMIR: %[[imul2:.*]] = mul nsw i64 %[[imul1]], 1
! LLVMIR: %[[iadd:.*]] = add nsw i64 %[[imul2]], 0
! LLVMIR: %[[gep1:.*]] = getelementptr <4 x float>, ptr %2, i64 %[[iadd]]
! LLVMIR: %[[arg1:.*]] = load <4 x float>, ptr %0, align 16
! LLVMIR: %[[arg2:.*]] = load i16, ptr %1, align 2
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