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[Hexagon] Flip subreg bit for reverse pairs hvx .new #75873

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Merged
merged 2 commits into from
Jan 18, 2024
Merged

[Hexagon] Flip subreg bit for reverse pairs hvx .new #75873

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c511435
[Hexagon] Flip subreg bit for reverse pairs hvx .new
quic-akaryaki Dec 18, 2023
50ce850
Use `-triple` instead of `-arch`.
quic-akaryaki Jan 17, 2024
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2 changes: 2 additions & 0 deletions llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -512,6 +512,8 @@ DecodeStatus HexagonDisassembler::getSingleInstruction(MCInst &MI, MCInst &MCB,
const bool Rev = HexagonMCInstrInfo::IsReverseVecRegPair(Producer);
const unsigned ProdPairIndex =
Rev ? Producer - Hexagon::WR0 : Producer - Hexagon::W0;
if (Rev)
SubregBit = !SubregBit;
Producer = (ProdPairIndex << 1) + SubregBit + Hexagon::V0;
} else if (SubregBit)
// Hexagon PRM 10.11 New-value operands
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6 changes: 4 additions & 2 deletions llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp
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Expand Up @@ -1036,8 +1036,10 @@ unsigned HexagonMCInstrInfo::SubregisterBit(unsigned Consumer,
unsigned Producer2) {
// If we're a single vector consumer of a double producer, set subreg bit
// based on if we're accessing the lower or upper register component
if (IsVecRegPair(Producer) && IsVecRegSingle(Consumer))
return (Consumer - Hexagon::V0) & 0x1;
if (IsVecRegPair(Producer) && IsVecRegSingle(Consumer)) {
unsigned Rev = IsReverseVecRegPair(Producer);
return ((Consumer - Hexagon::V0) & 0x1) ^ Rev;
}
if (Producer2 != Hexagon::NoRegister)
return Consumer == Producer;
return 0;
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18 changes: 18 additions & 0 deletions llvm/test/MC/Hexagon/hvx-nv-pair-reverse.s
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@@ -0,0 +1,18 @@
# RUN: llvm-mc -triple=hexagon -mv69 -mhvx -filetype=obj %s | \
# RUN: llvm-objdump --triple=hexagon --mcpu=hexagonv69 --mattr=+hvx -d - | \
# RUN: FileCheck %s
# CHECK: 00000000 <.text>:

{
V4:5.w = vadd(V1:0.w, V3:2.w)
vmem(r0+#0) = v4.new
}
# CHECK-NEXT: 1c6240c5 { v4:5.w = vadd(v1:0.w,v3:2.w)
# CHECK-NEXT: 2820c023 vmem(r0+#0x0) = v4.new }

{
V4:5.w = vadd(V1:0.w, V3:2.w)
vmem(r0+#0) = v5.new
}
# CHECK-NEXT: 1c6240c5 { v4:5.w = vadd(v1:0.w,v3:2.w)
# CHECK-NEXT: 2820c022 vmem(r0+#0x0) = v5.new }