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[RISCV][NFC] Refine MCOperandPredicate code for rtlist. #76028

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Merged
merged 1 commit into from
Dec 26, 2023

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yetingk
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@yetingk yetingk commented Dec 20, 2023

(Imm <= 15) could be implied by isUInt<4>(Imm).

(Imm <= 15) could be implied by isUInt<4>(Imm).
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llvmbot commented Dec 20, 2023

@llvm/pr-subscribers-backend-risc-v

Author: Yeting Kuo (yetingk)

Changes

(Imm <= 15) could be implied by isUInt<4>(Imm).


Full diff: https://github.com/llvm/llvm-project/pull/76028.diff

1 Files Affected:

  • (modified) llvm/lib/Target/RISCV/RISCVInstrInfoZc.td (+1-2)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
index a78f3624446871..9a7249fe3e3d6c 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
@@ -56,9 +56,8 @@ def rlist : Operand<OtherVT> {
     int64_t Imm;
     if (!MCOp.evaluateAsConstantImm(Imm))
       return false;
-    if (!isUInt<4>(Imm)) return false;
     // 0~3 Reserved for EABI
-    return (Imm >= 4) && (Imm <= 15);
+    return isUInt<4>(Imm) && Imm >= 4;
   }];
  }
 

@yetingk yetingk requested a review from tclin914 December 21, 2023 14:08
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yetingk commented Dec 26, 2023

Ping.

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LGTM

@yetingk yetingk merged commit b996f84 into llvm:main Dec 26, 2023
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3 participants