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[RISCV][MC] Add support for experimental Zcmop extension #76395

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Merged
merged 3 commits into from
Dec 28, 2023
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[RISCV][MC] Add support for experimental Zcmop extension #76395

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20fd01b
[RISCV][MC] Add support for experimental Zcmop extension
wangpc-pp Dec 26, 2023
d77c26a
Add implied extensions to RISCVISAInfo.cpp and remove leading spaces
wangpc-pp Dec 27, 2023
84a6bab
Fix copy-paste error in tests
wangpc-pp Dec 27, 2023
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9 changes: 9 additions & 0 deletions clang/test/Preprocessor/riscv-target-features.c
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Expand Up @@ -121,6 +121,7 @@
// CHECK-NOT: __riscv_zicfilp {{.*$}}
// CHECK-NOT: __riscv_zicond {{.*$}}
// CHECK-NOT: __riscv_zimop {{.*$}}
// CHECK-NOT: __riscv_zcmop {{.*$}}
// CHECK-NOT: __riscv_ztso {{.*$}}
// CHECK-NOT: __riscv_zvbb {{.*$}}
// CHECK-NOT: __riscv_zvbc {{.*$}}
Expand Down Expand Up @@ -1080,6 +1081,14 @@
// RUN: -o - | FileCheck --check-prefix=CHECK-ZIMOP-EXT %s
// CHECK-ZIMOP-EXT: __riscv_zimop 1000{{$}}

// RUN: %clang --target=riscv32 -menable-experimental-extensions \
// RUN: -march=rv32i_zcmop0p2 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZCMOP-EXT %s
// RUN: %clang --target=riscv64 -menable-experimental-extensions \
// RUN: -march=rv64i_zcmop0p2 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZCMOP-EXT %s
// CHECK-ZCMOP-EXT: __riscv_zcmop 2000{{$}}

// RUN: %clang --target=riscv32-unknown-linux-gnu -menable-experimental-extensions \
// RUN: -march=rv32iztso0p1 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZTSO-EXT %s
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3 changes: 3 additions & 0 deletions llvm/docs/RISCVUsage.rst
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Expand Up @@ -224,6 +224,9 @@ The primary goal of experimental support is to assist in the process of ratifica
``experimental-zimop``
LLVM implements the `v0.1 proposed specification <https://github.com/riscv/riscv-isa-manual/blob/main/src/zimop.adoc>`__.

``experimental-zcmop``
LLVM implements the `v0.2 proposed specification <https://github.com/riscv/riscv-isa-manual/blob/main/src/zimop.adoc>`__.

To use an experimental extension from `clang`, you must add `-menable-experimental-extensions` to the command line, and specify the exact version of the experimental extension you are using. To use an experimental extension with LLVM's internal developer tools (e.g. `llc`, `llvm-objdump`, `llvm-mc`), you must prefix the extension name with `experimental-`. Note that you don't need to specify the version with internal tools, and shouldn't include the `experimental-` prefix with `clang`.

Vendor Extensions
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4 changes: 4 additions & 0 deletions llvm/lib/Support/RISCVISAInfo.cpp
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Expand Up @@ -191,6 +191,8 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
{"zacas", RISCVExtensionVersion{1, 0}},

{"zcmop", RISCVExtensionVersion{0, 2}},

{"zfbfmin", RISCVExtensionVersion{0, 8}},

{"zicfilp", RISCVExtensionVersion{0, 4}},
Expand Down Expand Up @@ -1008,6 +1010,7 @@ static const char *ImpliedExtsZcb[] = {"zca"};
static const char *ImpliedExtsZcd[] = {"d", "zca"};
static const char *ImpliedExtsZce[] = {"zcb", "zcmp", "zcmt"};
static const char *ImpliedExtsZcf[] = {"f", "zca"};
static const char *ImpliedExtsZcmop[] = {"zca"};
static const char *ImpliedExtsZcmp[] = {"zca"};
static const char *ImpliedExtsZcmt[] = {"zca", "zicsr"};
static const char *ImpliedExtsZdinx[] = {"zfinx"};
Expand Down Expand Up @@ -1080,6 +1083,7 @@ static constexpr ImpliedExtsEntry ImpliedExts[] = {
{{"zcd"}, {ImpliedExtsZcd}},
{{"zce"}, {ImpliedExtsZce}},
{{"zcf"}, {ImpliedExtsZcf}},
{{"zcmop"}, {ImpliedExtsZcmop}},
{{"zcmp"}, {ImpliedExtsZcmp}},
{{"zcmt"}, {ImpliedExtsZcmt}},
{{"zdinx"}, {ImpliedExtsZdinx}},
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7 changes: 7 additions & 0 deletions llvm/lib/Target/RISCV/RISCVFeatures.td
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Expand Up @@ -693,6 +693,13 @@ def HasStdExtZimop : Predicate<"Subtarget->hasStdExtZimop()">,
AssemblerPredicate<(all_of FeatureStdExtZimop),
"'Zimop' (May-Be-Operations)">;

def FeatureStdExtZcmop : SubtargetFeature<"experimental-zcmop", "HasStdExtZcmop", "true",
"'Zcmop' (Compressed May-Be-Operations)",
[FeatureStdExtZca]>;
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The spec says Zcmop requires Zca. Is this means Zcmop imply Zca? I am not sure with this.

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I think so. The specs have been very inconsistent on terminology. The fundamental issue is that the specs define hardware and don't think about how -march in tools works. What the spec is saying is that if your hardware supports Zcmop, it must support Zca.

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My understanding for those terminology on RISC-V ISA spec is: imply == depend == require

See comment from Krste and Andrew in this issue: riscvarchive/riscv-v-spec#723 (comment)

def HasStdExtZcmop : Predicate<"Subtarget->hasStdExtZcmop()">,
AssemblerPredicate<(all_of FeatureStdExtZcmop),
"'Zcmop' (Compressed May-Be-Operations)">;

def FeatureStdExtSmaia
: SubtargetFeature<"smaia", "HasStdExtSmaia", "true",
"'Smaia' (Smaia encompasses all added CSRs and all "
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1 change: 1 addition & 0 deletions llvm/lib/Target/RISCV/RISCVInstrInfo.td
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Expand Up @@ -2146,6 +2146,7 @@ include "RISCVInstrInfoZicond.td"
// Compressed
include "RISCVInstrInfoC.td"
include "RISCVInstrInfoZc.td"
include "RISCVInstrInfoZcmop.td"

//===----------------------------------------------------------------------===//
// Vendor extensions
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30 changes: 30 additions & 0 deletions llvm/lib/Target/RISCV/RISCVInstrInfoZcmop.td
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@@ -0,0 +1,30 @@
//===-- RISCVInstrInfoZcmop.td -----------------------------*- tablegen -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This file describes the RISC-V instructions from the standard Compressed
// May-Be-Operations Extension (Zcmop).
// This version is still experimental as the 'Zcmop' extension hasn't been
// ratified yet. It is based on v0.2 of the specification.
//
//===----------------------------------------------------------------------===//

let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
class CMOPInst<bits<3> imm3, string opcodestr>
: RVInst16CI<0b011, 0b01, (outs), (ins), opcodestr, ""> {
let Inst{6-2} = 0;
let Inst{7} = 1;
let Inst{10-8} = imm3;
let Inst{12-11} = 0;
}

foreach i = 0...7 in {
let Predicates = [HasStdExtZcmop] in {
defvar n = !add(!mul(i, 2), 1);
def CMOP # n : CMOPInst<i, "cmop." # n>, Sched<[]>;
} // Predicates = [HasStdExtZcmop]
}
4 changes: 4 additions & 0 deletions llvm/test/CodeGen/RISCV/attributes.ll
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Expand Up @@ -86,6 +86,7 @@
; RUN: llc -mtriple=riscv32 -mattr=+zvfh %s -o - | FileCheck --check-prefix=RV32ZVFH %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zicond %s -o - | FileCheck --check-prefix=RV32ZICOND %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zimop %s -o - | FileCheck --check-prefix=RV32ZIMOP %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zcmop %s -o - | FileCheck --check-prefix=RV32ZCMOP %s
; RUN: llc -mtriple=riscv32 -mattr=+smaia %s -o - | FileCheck --check-prefixes=CHECK,RV32SMAIA %s
; RUN: llc -mtriple=riscv32 -mattr=+ssaia %s -o - | FileCheck --check-prefixes=CHECK,RV32SSAIA %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV32ZFBFMIN %s
Expand Down Expand Up @@ -179,6 +180,7 @@
; RUN: llc -mtriple=riscv64 -mattr=+zvfh %s -o - | FileCheck --check-prefix=RV64ZVFH %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zicond %s -o - | FileCheck --check-prefix=RV64ZICOND %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zimop %s -o - | FileCheck --check-prefix=RV64ZIMOP %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zcmop %s -o - | FileCheck --check-prefix=RV64ZCMOP %s
; RUN: llc -mtriple=riscv64 -mattr=+smaia %s -o - | FileCheck --check-prefixes=CHECK,RV64SMAIA %s
; RUN: llc -mtriple=riscv64 -mattr=+ssaia %s -o - | FileCheck --check-prefixes=CHECK,RV64SSAIA %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV64ZFBFMIN %s
Expand Down Expand Up @@ -274,6 +276,7 @@
; RV32ZVFH: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfhmin1p0_zve32f1p0_zve32x1p0_zvfh1p0_zvfhmin1p0_zvl32b1p0"
; RV32ZICOND: .attribute 5, "rv32i2p1_zicond1p0"
; RV32ZIMOP: .attribute 5, "rv32i2p1_zimop0p1"
; RV32ZCMOP: .attribute 5, "rv32i2p1_zca1p0_zcmop0p2"
; RV32SMAIA: .attribute 5, "rv32i2p1_smaia1p0"
; RV32SSAIA: .attribute 5, "rv32i2p1_ssaia1p0"
; RV32ZFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin0p8"
Expand Down Expand Up @@ -366,6 +369,7 @@
; RV64ZVFH: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfhmin1p0_zve32f1p0_zve32x1p0_zvfh1p0_zvfhmin1p0_zvl32b1p0"
; RV64ZICOND: .attribute 5, "rv64i2p1_zicond1p0"
; RV64ZIMOP: .attribute 5, "rv64i2p1_zimop0p1"
; RV64ZCMOP: .attribute 5, "rv64i2p1_zca1p0_zcmop0p2"
; RV64SMAIA: .attribute 5, "rv64i2p1_smaia1p0"
; RV64SSAIA: .attribute 5, "rv64i2p1_ssaia1p0"
; RV64ZFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin0p8"
Expand Down
7 changes: 7 additions & 0 deletions llvm/test/MC/RISCV/rv32zcmop-invalid.s
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@@ -0,0 +1,7 @@
# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zcmop < %s 2>&1 | FileCheck %s

cmop.0 # CHECK: :[[@LINE]]:1: error: unrecognized instruction mnemonic

cmop.1 t0 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction

cmop.1 0x0 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
42 changes: 42 additions & 0 deletions llvm/test/MC/RISCV/rvzcmop-valid.s
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@@ -0,0 +1,42 @@
# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zcmop -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zcmop -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zcmop < %s \
# RUN: | llvm-objdump --mattr=+experimental-zcmop -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zcmop < %s \
# RUN: | llvm-objdump --mattr=+experimental-zcmop -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s

# CHECK-ASM-AND-OBJ: cmop.1
# CHECK-ASM: encoding: [0x81,0x60]
cmop.1

# CHECK-ASM-AND-OBJ: cmop.3
# CHECK-ASM: encoding: [0x81,0x61]
cmop.3

# CHECK-ASM-AND-OBJ: cmop.5
# CHECK-ASM: encoding: [0x81,0x62]
cmop.5

# CHECK-ASM-AND-OBJ: cmop.7
# CHECK-ASM: encoding: [0x81,0x63]
cmop.7

# CHECK-ASM-AND-OBJ: cmop.9
# CHECK-ASM: encoding: [0x81,0x64]
cmop.9

# CHECK-ASM-AND-OBJ: cmop.11
# CHECK-ASM: encoding: [0x81,0x65]
cmop.11

# CHECK-ASM-AND-OBJ: cmop.13
# CHECK-ASM: encoding: [0x81,0x66]
cmop.13

# CHECK-ASM-AND-OBJ: cmop.15
# CHECK-ASM: encoding: [0x81,0x67]
cmop.15
1 change: 1 addition & 0 deletions llvm/unittests/Support/RISCVISAInfoTest.cpp
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Expand Up @@ -759,6 +759,7 @@ Experimental extensions
zimop 0.1
zacas 1.0
zfbfmin 0.8
zcmop 0.2
ztso 0.1
zvfbfmin 0.8
zvfbfwma 0.8
Expand Down