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[AMDGPU][True16] Don't use the VGPR_LO/HI16 register classes. #76440

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Merged
merged 1 commit into from
Dec 28, 2023
Merged

[AMDGPU][True16] Don't use the VGPR_LO/HI16 register classes. #76440

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2 changes: 1 addition & 1 deletion llvm/lib/Target/AMDGPU/AMDGPURegisterBanks.td
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Original file line number Diff line number Diff line change
Expand Up @@ -11,7 +11,7 @@ def SGPRRegBank : RegisterBank<"SGPR",
>;

def VGPRRegBank : RegisterBank<"VGPR",
[VGPR_LO16, VGPR_HI16, VGPR_32, VReg_64, VReg_96, VReg_128, VReg_160, VReg_192, VReg_224, VReg_256, VReg_288, VReg_320, VReg_352, VReg_384, VReg_512, VReg_1024]
[VGPR_32, VReg_64, VReg_96, VReg_128, VReg_160, VReg_192, VReg_224, VReg_256, VReg_288, VReg_320, VReg_352, VReg_384, VReg_512, VReg_1024]
>;

// It is helpful to distinguish conditions from ordinary SGPRs.
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3 changes: 1 addition & 2 deletions llvm/lib/Target/AMDGPU/AMDGPUResourceUsageAnalysis.cpp
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Expand Up @@ -346,8 +346,7 @@ AMDGPUResourceUsageAnalysis::analyzeResourceUsage(
IsSGPR = true;
Width = 1;
} else if (AMDGPU::VGPR_32RegClass.contains(Reg) ||
AMDGPU::VGPR_LO16RegClass.contains(Reg) ||
AMDGPU::VGPR_HI16RegClass.contains(Reg)) {
AMDGPU::VGPR_16RegClass.contains(Reg)) {
IsSGPR = false;
Width = 1;
} else if (AMDGPU::AGPR_32RegClass.contains(Reg) ||
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5 changes: 2 additions & 3 deletions llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
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Expand Up @@ -1284,9 +1284,8 @@ MCOperand AMDGPUDisassembler::createSRegOperand(unsigned SRegClassID,

MCOperand AMDGPUDisassembler::createVGPR16Operand(unsigned RegIdx,
bool IsHi) const {
unsigned RCID =
IsHi ? AMDGPU::VGPR_HI16RegClassID : AMDGPU::VGPR_LO16RegClassID;
return createRegOperand(RCID, RegIdx);
unsigned RegIdxInVGPR16 = RegIdx * 2 + (IsHi ? 1 : 0);
return createRegOperand(AMDGPU::VGPR_16RegClassID, RegIdxInVGPR16);
}

// Decode Literals for insts which always have a literal in the encoding
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8 changes: 2 additions & 6 deletions llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
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Expand Up @@ -955,12 +955,8 @@ void SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
bool IsSGPRSrc = AMDGPU::SReg_LO16RegClass.contains(SrcReg);
bool IsAGPRDst = AMDGPU::AGPR_LO16RegClass.contains(DestReg);
bool IsAGPRSrc = AMDGPU::AGPR_LO16RegClass.contains(SrcReg);
bool DstLow = AMDGPU::VGPR_LO16RegClass.contains(DestReg) ||
AMDGPU::SReg_LO16RegClass.contains(DestReg) ||
AMDGPU::AGPR_LO16RegClass.contains(DestReg);
bool SrcLow = AMDGPU::VGPR_LO16RegClass.contains(SrcReg) ||
AMDGPU::SReg_LO16RegClass.contains(SrcReg) ||
AMDGPU::AGPR_LO16RegClass.contains(SrcReg);
bool DstLow = !AMDGPU::isHi(DestReg, RI);
bool SrcLow = !AMDGPU::isHi(SrcReg, RI);
MCRegister NewDestReg = RI.get32BitRegister(DestReg);
MCRegister NewSrcReg = RI.get32BitRegister(SrcReg);

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10 changes: 4 additions & 6 deletions llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
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Expand Up @@ -330,8 +330,10 @@ SIRegisterInfo::SIRegisterInfo(const GCNSubtarget &ST)

RegPressureIgnoredUnits.resize(getNumRegUnits());
RegPressureIgnoredUnits.set(*regunits(MCRegister::from(AMDGPU::M0)).begin());
for (auto Reg : AMDGPU::VGPR_HI16RegClass)
RegPressureIgnoredUnits.set(*regunits(Reg).begin());
for (auto Reg : AMDGPU::VGPR_16RegClass) {
if (AMDGPU::isHi(Reg, *this))
RegPressureIgnoredUnits.set(*regunits(Reg).begin());
}

// HACK: Until this is fully tablegen'd.
static llvm::once_flag InitializeRegSplitPartsFlag;
Expand Down Expand Up @@ -2808,8 +2810,6 @@ getAlignedVectorSuperClassForBitWidth(unsigned BitWidth) {

const TargetRegisterClass *
SIRegisterInfo::getVectorSuperClassForBitWidth(unsigned BitWidth) const {
if (BitWidth == 16)
return &AMDGPU::VGPR_LO16RegClass;
Comment on lines -2811 to -2812
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Looks like this if and the removed cases below were always dead code.

if (BitWidth == 32)
return &AMDGPU::AV_32RegClass;
return ST.needsAlignedVGPRs()
Expand Down Expand Up @@ -3041,8 +3041,6 @@ unsigned SIRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
default:
return AMDGPUGenRegisterInfo::getRegPressureLimit(RC, MF);
case AMDGPU::VGPR_32RegClassID:
case AMDGPU::VGPR_LO16RegClassID:
case AMDGPU::VGPR_HI16RegClassID:
return std::min(ST.getMaxNumVGPRs(Occupancy), ST.getMaxNumVGPRs(MF));
case AMDGPU::SGPR_32RegClassID:
case AMDGPU::SGPR_LO16RegClassID:
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2 changes: 0 additions & 2 deletions llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
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Expand Up @@ -2296,8 +2296,6 @@ bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo) {
// (move from MC* level to Target* level). Return size in bits.
unsigned getRegBitWidth(unsigned RCID) {
switch (RCID) {
case AMDGPU::VGPR_LO16RegClassID:
case AMDGPU::VGPR_HI16RegClassID:
case AMDGPU::SGPR_LO16RegClassID:
case AMDGPU::AGPR_LO16RegClassID:
return 16;
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