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[RISCV] Remove gp and tp from callee saved register lists. #76483

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Merged
merged 1 commit into from
Dec 28, 2023
Merged

[RISCV] Remove gp and tp from callee saved register lists. #76483

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4 changes: 2 additions & 2 deletions llvm/lib/Target/RISCV/RISCVCallingConv.td
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Original file line number Diff line number Diff line change
Expand Up @@ -14,7 +14,7 @@
// RISCVISelLowering.cpp (CC_RISCV).

def CSR_ILP32_LP64
: CalleeSavedRegs<(add X1, X3, X4, X8, X9, (sequence "X%u", 18, 27))>;
: CalleeSavedRegs<(add X1, X8, X9, (sequence "X%u", 18, 27))>;

def CSR_ILP32F_LP64F
: CalleeSavedRegs<(add CSR_ILP32_LP64,
Expand All @@ -29,7 +29,7 @@ def CSR_NoRegs : CalleeSavedRegs<(add)>;

// Interrupt handler needs to save/restore all registers that are used,
// both Caller and Callee saved registers.
def CSR_Interrupt : CalleeSavedRegs<(add X1, (sequence "X%u", 3, 31))>;
def CSR_Interrupt : CalleeSavedRegs<(add X1, (sequence "X%u", 5, 31))>;

// Same as CSR_Interrupt, but including all 32-bit FP registers.
def CSR_XLEN_F32_Interrupt: CalleeSavedRegs<(add CSR_Interrupt,
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32 changes: 0 additions & 32 deletions llvm/test/CodeGen/RISCV/inline-asm-abi-names.ll
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Expand Up @@ -156,26 +156,18 @@ define i32 @explicit_register_sp(i32 %a) nounwind {
define i32 @explicit_register_x3(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_x3:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw gp, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv gp, a0
; RV32I-NEXT: #APP
; RV32I-NEXT: addi a0, gp, 0
; RV32I-NEXT: #NO_APP
; RV32I-NEXT: lw gp, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV64I-LABEL: explicit_register_x3:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd gp, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv gp, a0
; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, gp, 0
; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ld gp, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{x3}"(i32 %a)
ret i32 %1
Expand All @@ -185,26 +177,18 @@ define i32 @explicit_register_x3(i32 %a) nounwind {
define i32 @explicit_register_gp(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_gp:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw gp, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv gp, a0
; RV32I-NEXT: #APP
; RV32I-NEXT: addi a0, gp, 0
; RV32I-NEXT: #NO_APP
; RV32I-NEXT: lw gp, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV64I-LABEL: explicit_register_gp:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd gp, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv gp, a0
; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, gp, 0
; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ld gp, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{gp}"(i32 %a)
ret i32 %1
Expand All @@ -214,26 +198,18 @@ define i32 @explicit_register_gp(i32 %a) nounwind {
define i32 @explicit_register_x4(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_x4:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw tp, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv tp, a0
; RV32I-NEXT: #APP
; RV32I-NEXT: addi a0, tp, 0
; RV32I-NEXT: #NO_APP
; RV32I-NEXT: lw tp, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV64I-LABEL: explicit_register_x4:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd tp, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv tp, a0
; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, tp, 0
; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ld tp, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{x4}"(i32 %a)
ret i32 %1
Expand All @@ -243,26 +219,18 @@ define i32 @explicit_register_x4(i32 %a) nounwind {
define i32 @explicit_register_tp(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_tp:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw tp, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv tp, a0
; RV32I-NEXT: #APP
; RV32I-NEXT: addi a0, tp, 0
; RV32I-NEXT: #NO_APP
; RV32I-NEXT: lw tp, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV64I-LABEL: explicit_register_tp:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd tp, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv tp, a0
; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, tp, 0
; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ld tp, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{tp}"(i32 %a)
ret i32 %1
Expand Down
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