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[DAG] Extend input types if needed in combineShiftToAVG. #76791

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Merged
merged 1 commit into from
Jan 3, 2024
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[DAG] Extend input types if needed in combineShiftToAVG. #76791

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7 changes: 3 additions & 4 deletions llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1064,10 +1064,9 @@ static SDValue combineShiftToAVG(SDValue Op, SelectionDAG &DAG,

SDLoc DL(Op);
SDValue ResultAVG =
DAG.getNode(AVGOpc, DL, NVT, DAG.getNode(ISD::TRUNCATE, DL, NVT, ExtOpA),
DAG.getNode(ISD::TRUNCATE, DL, NVT, ExtOpB));
return DAG.getNode(IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, DL, VT,
ResultAVG);
DAG.getNode(AVGOpc, DL, NVT, DAG.getExtOrTrunc(IsSigned, ExtOpA, DL, NVT),
DAG.getExtOrTrunc(IsSigned, ExtOpB, DL, NVT));
return DAG.getExtOrTrunc(IsSigned, ResultAVG, DL, VT);
}

/// Look at Op. At this point, we know that only the OriginalDemandedBits of the
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18 changes: 18 additions & 0 deletions llvm/test/CodeGen/AArch64/arm64-vhadd.ll
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Expand Up @@ -1392,6 +1392,24 @@ define <8 x i8> @sextmask3v8i8(<8 x i16> %src1, <8 x i8> %src2) {
ret <8 x i8> %result
}

define <4 x i16> @ext_via_i19(<4 x i16> %a) {
; CHECK-LABEL: ext_via_i19:
; CHECK: // %bb.0:
; CHECK-NEXT: movi.4s v1, #1
; CHECK-NEXT: uaddw.4s v0, v1, v0
; CHECK-NEXT: uhadd.4s v0, v0, v1
; CHECK-NEXT: xtn.4h v0, v0
; CHECK-NEXT: ret
%t3 = zext <4 x i16> %a to <4 x i32>
%t4 = add <4 x i32> %t3, <i32 1, i32 1, i32 1, i32 1>
%t5 = trunc <4 x i32> %t4 to <4 x i19>
%new0 = add <4 x i19> %t5, <i19 1, i19 1, i19 1, i19 1>
%new1 = lshr <4 x i19> %new0, <i19 1, i19 1, i19 1, i19 1>
%last = zext <4 x i19> %new1 to <4 x i32>
%t6 = trunc <4 x i32> %last to <4 x i16>
ret <4 x i16> %t6
}

declare <8 x i8> @llvm.aarch64.neon.srhadd.v8i8(<8 x i8>, <8 x i8>)
declare <4 x i16> @llvm.aarch64.neon.srhadd.v4i16(<4 x i16>, <4 x i16>)
declare <2 x i32> @llvm.aarch64.neon.srhadd.v2i32(<2 x i32>, <2 x i32>)
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