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[RISCV][GlobalISel] Zbkb support for G_BSWAP #77050

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Merged
merged 4 commits into from
Jan 6, 2024
Merged

[RISCV][GlobalISel] Zbkb support for G_BSWAP #77050

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65fc6f3
[RISCV][GlobalISel] Zbkb support for G_BSWAP
mgudim Jan 5, 2024
a5dc534
Changed some filckeck prefixes to default "CHECK".
mgudim Jan 5, 2024
283702d
Put run commands on the same line.
mgudim Jan 5, 2024
32b6b53
Empty commit to restart CI.
mgudim Jan 6, 2024
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2 changes: 1 addition & 1 deletion llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -113,7 +113,7 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
getActionDefinitionsBuilder(G_BITREVERSE).maxScalar(0, sXLen).lower();

auto &BSWAPActions = getActionDefinitionsBuilder(G_BSWAP);
if (ST.hasStdExtZbb())
if (ST.hasStdExtZbb() || ST.hasStdExtZbkb())
BSWAPActions.legalFor({sXLen}).clampScalar(0, sXLen, sXLen);
else
BSWAPActions.maxScalar(0, sXLen).lower();
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15 changes: 8 additions & 7 deletions llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/bswap-rv32.mir
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@@ -1,19 +1,20 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -mattr=+zbb -run-pass=instruction-select \
# RUN: -simplify-mir -verify-machineinstrs %s -o - \
# RUN: | FileCheck -check-prefix=RV32I %s
# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
# RUN: llc -mtriple=riscv32 -mattr=+zbkb -run-pass=instruction-select \
# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s

---
name: bswap_s32
legalized: true
regBankSelected: true
body: |
bb.0.entry:
; RV32I-LABEL: name: bswap_s32
; RV32I: [[COPY:%[0-9]+]]:gpr = COPY $x10
; RV32I-NEXT: [[REV8_RV32_:%[0-9]+]]:gpr = REV8_RV32 [[COPY]]
; RV32I-NEXT: $x10 = COPY [[REV8_RV32_]]
; RV32I-NEXT: PseudoRET implicit $x10
; CHECK-LABEL: name: bswap_s32
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $x10
; CHECK-NEXT: [[REV8_RV32_:%[0-9]+]]:gpr = REV8_RV32 [[COPY]]
; CHECK-NEXT: $x10 = COPY [[REV8_RV32_]]
; CHECK-NEXT: PseudoRET implicit $x10
%0:gprb(s32) = COPY $x10
%1:gprb(s32) = G_BSWAP %0
$x10 = COPY %1(s32)
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15 changes: 8 additions & 7 deletions llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/bswap-rv64.mir
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@@ -1,19 +1,20 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv64 -mattr=+zbb -run-pass=instruction-select \
# RUN: -simplify-mir -verify-machineinstrs %s -o - \
# RUN: | FileCheck -check-prefix=RV64I %s
# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
# RUN: llc -mtriple=riscv64 -mattr=+zbkb -run-pass=instruction-select \
# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s

---
name: bswap_s64
legalized: true
regBankSelected: true
body: |
bb.0.entry:
; RV64I-LABEL: name: bswap_s64
; RV64I: [[COPY:%[0-9]+]]:gpr = COPY $x10
; RV64I-NEXT: [[REV8_RV64_:%[0-9]+]]:gpr = REV8_RV64 [[COPY]]
; RV64I-NEXT: $x10 = COPY [[REV8_RV64_]]
; RV64I-NEXT: PseudoRET implicit $x10
; CHECK-LABEL: name: bswap_s64
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $x10
; CHECK-NEXT: [[REV8_RV64_:%[0-9]+]]:gpr = REV8_RV64 [[COPY]]
; CHECK-NEXT: $x10 = COPY [[REV8_RV64_]]
; CHECK-NEXT: PseudoRET implicit $x10
%0:gprb(s64) = COPY $x10
%1:gprb(s64) = G_BSWAP %0
$x10 = COPY %1(s64)
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58 changes: 30 additions & 28 deletions llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-bswap-rv32.mir
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Expand Up @@ -2,7 +2,9 @@
# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - \
# RUN: | FileCheck %s --check-prefix=RV32I
# RUN: llc -mtriple=riscv32 -mattr=+zbb -run-pass=legalizer %s -o - \
# RUN: | FileCheck %s --check-prefix=RV32ZBB
# RUN: | FileCheck %s --check-prefix=RV32ZBB_OR_RV32ZBKB
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I think these can be simplified to CHECK?

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We are checking generated code in two scenarios: when zbb or zbkb is present and when it's not. So I think having these descriptions in the prefix is good.

# RUN: llc -mtriple=riscv32 -mattr=+zbkb -run-pass=legalizer %s -o - \
# RUN: | FileCheck %s --check-prefix=RV32ZBB_OR_RV32ZBKB

---
name: bswap_i16
Expand All @@ -23,16 +25,16 @@ body: |
; RV32I-NEXT: $x10 = COPY [[AND]](s32)
; RV32I-NEXT: PseudoRET implicit $x10
;
; RV32ZBB-LABEL: name: bswap_i16
; RV32ZBB: liveins: $x10
; RV32ZBB-NEXT: {{ $}}
; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
; RV32ZBB-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY]], 16
; RV32ZBB-NEXT: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[ASSERT_ZEXT]]
; RV32ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; RV32ZBB-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BSWAP]], [[C]](s32)
; RV32ZBB-NEXT: $x10 = COPY [[LSHR]](s32)
; RV32ZBB-NEXT: PseudoRET implicit $x10
; RV32ZBB_OR_RV32ZBKB-LABEL: name: bswap_i16
; RV32ZBB_OR_RV32ZBKB: liveins: $x10
; RV32ZBB_OR_RV32ZBKB-NEXT: {{ $}}
; RV32ZBB_OR_RV32ZBKB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
; RV32ZBB_OR_RV32ZBKB-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY]], 16
; RV32ZBB_OR_RV32ZBKB-NEXT: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[ASSERT_ZEXT]]
; RV32ZBB_OR_RV32ZBKB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; RV32ZBB_OR_RV32ZBKB-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BSWAP]], [[C]](s32)
; RV32ZBB_OR_RV32ZBKB-NEXT: $x10 = COPY [[LSHR]](s32)
; RV32ZBB_OR_RV32ZBKB-NEXT: PseudoRET implicit $x10
%0:_(s32) = COPY $x10
%1:_(s32) = G_ASSERT_ZEXT %0, 16
%2:_(s16) = G_TRUNC %1(s32)
Expand Down Expand Up @@ -65,13 +67,13 @@ body: |
; RV32I-NEXT: $x10 = COPY [[OR2]](s32)
; RV32I-NEXT: PseudoRET implicit $x10
;
; RV32ZBB-LABEL: name: bswap_i32
; RV32ZBB: liveins: $x10
; RV32ZBB-NEXT: {{ $}}
; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
; RV32ZBB-NEXT: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[COPY]]
; RV32ZBB-NEXT: $x10 = COPY [[BSWAP]](s32)
; RV32ZBB-NEXT: PseudoRET implicit $x10
; RV32ZBB_OR_RV32ZBKB-LABEL: name: bswap_i32
; RV32ZBB_OR_RV32ZBKB: liveins: $x10
; RV32ZBB_OR_RV32ZBKB-NEXT: {{ $}}
; RV32ZBB_OR_RV32ZBKB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
; RV32ZBB_OR_RV32ZBKB-NEXT: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[COPY]]
; RV32ZBB_OR_RV32ZBKB-NEXT: $x10 = COPY [[BSWAP]](s32)
; RV32ZBB_OR_RV32ZBKB-NEXT: PseudoRET implicit $x10
%0:_(s32) = COPY $x10
%1:_(s32) = G_BSWAP %0
$x10 = COPY %1(s32)
Expand Down Expand Up @@ -115,16 +117,16 @@ body: |
; RV32I-NEXT: $x11 = COPY [[OR5]](s32)
; RV32I-NEXT: PseudoRET implicit $x10, implicit $x11
;
; RV32ZBB-LABEL: name: bswap_i64
; RV32ZBB: liveins: $x10, $x11
; RV32ZBB-NEXT: {{ $}}
; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
; RV32ZBB-NEXT: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[COPY1]]
; RV32ZBB-NEXT: [[BSWAP1:%[0-9]+]]:_(s32) = G_BSWAP [[COPY]]
; RV32ZBB-NEXT: $x10 = COPY [[BSWAP]](s32)
; RV32ZBB-NEXT: $x11 = COPY [[BSWAP1]](s32)
; RV32ZBB-NEXT: PseudoRET implicit $x10, implicit $x11
; RV32ZBB_OR_RV32ZBKB-LABEL: name: bswap_i64
; RV32ZBB_OR_RV32ZBKB: liveins: $x10, $x11
; RV32ZBB_OR_RV32ZBKB-NEXT: {{ $}}
; RV32ZBB_OR_RV32ZBKB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
; RV32ZBB_OR_RV32ZBKB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
; RV32ZBB_OR_RV32ZBKB-NEXT: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[COPY1]]
; RV32ZBB_OR_RV32ZBKB-NEXT: [[BSWAP1:%[0-9]+]]:_(s32) = G_BSWAP [[COPY]]
; RV32ZBB_OR_RV32ZBKB-NEXT: $x10 = COPY [[BSWAP]](s32)
; RV32ZBB_OR_RV32ZBKB-NEXT: $x11 = COPY [[BSWAP1]](s32)
; RV32ZBB_OR_RV32ZBKB-NEXT: PseudoRET implicit $x10, implicit $x11
%0:_(s32) = COPY $x10
%1:_(s32) = COPY $x11
%2:_(s64) = G_MERGE_VALUES %0(s32), %1(s32)
Expand Down
58 changes: 30 additions & 28 deletions llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-bswap-rv64.mir
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Expand Up @@ -2,7 +2,9 @@
# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - \
# RUN: | FileCheck %s --check-prefix=RV64I
# RUN: llc -mtriple=riscv64 -mattr=+zbb -run-pass=legalizer %s -o - \
# RUN: | FileCheck %s --check-prefix=RV64ZBB
# RUN: | FileCheck %s --check-prefix=RV64ZBB_OR_RV64ZBKB
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I think these can be simplified to CHECK?

# RUN: llc -mtriple=riscv64 -mattr=+zbkb -run-pass=legalizer %s -o - \
# RUN: | FileCheck %s --check-prefix=RV64ZBB_OR_RV64ZBKB

---
name: bswap_i16
Expand All @@ -27,16 +29,16 @@ body: |
; RV64I-NEXT: $x10 = COPY [[AND]](s64)
; RV64I-NEXT: PseudoRET implicit $x10
;
; RV64ZBB-LABEL: name: bswap_i16
; RV64ZBB: liveins: $x10
; RV64ZBB-NEXT: {{ $}}
; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; RV64ZBB-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s64) = G_ASSERT_ZEXT [[COPY]], 16
; RV64ZBB-NEXT: [[BSWAP:%[0-9]+]]:_(s64) = G_BSWAP [[ASSERT_ZEXT]]
; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
; RV64ZBB-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[BSWAP]], [[C]](s64)
; RV64ZBB-NEXT: $x10 = COPY [[LSHR]](s64)
; RV64ZBB-NEXT: PseudoRET implicit $x10
; RV64ZBB_OR_RV64ZBKB-LABEL: name: bswap_i16
; RV64ZBB_OR_RV64ZBKB: liveins: $x10
; RV64ZBB_OR_RV64ZBKB-NEXT: {{ $}}
; RV64ZBB_OR_RV64ZBKB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; RV64ZBB_OR_RV64ZBKB-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s64) = G_ASSERT_ZEXT [[COPY]], 16
; RV64ZBB_OR_RV64ZBKB-NEXT: [[BSWAP:%[0-9]+]]:_(s64) = G_BSWAP [[ASSERT_ZEXT]]
; RV64ZBB_OR_RV64ZBKB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
; RV64ZBB_OR_RV64ZBKB-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[BSWAP]], [[C]](s64)
; RV64ZBB_OR_RV64ZBKB-NEXT: $x10 = COPY [[LSHR]](s64)
; RV64ZBB_OR_RV64ZBKB-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
%1:_(s64) = G_ASSERT_ZEXT %0, 16
%2:_(s16) = G_TRUNC %1(s64)
Expand Down Expand Up @@ -74,16 +76,16 @@ body: |
; RV64I-NEXT: $x10 = COPY [[ZEXT]](s64)
; RV64I-NEXT: PseudoRET implicit $x10
;
; RV64ZBB-LABEL: name: bswap_i32
; RV64ZBB: liveins: $x10
; RV64ZBB-NEXT: {{ $}}
; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; RV64ZBB-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s64) = G_ASSERT_ZEXT [[COPY]], 32
; RV64ZBB-NEXT: [[BSWAP:%[0-9]+]]:_(s64) = G_BSWAP [[ASSERT_ZEXT]]
; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
; RV64ZBB-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[BSWAP]], [[C]](s64)
; RV64ZBB-NEXT: $x10 = COPY [[LSHR]](s64)
; RV64ZBB-NEXT: PseudoRET implicit $x10
; RV64ZBB_OR_RV64ZBKB-LABEL: name: bswap_i32
; RV64ZBB_OR_RV64ZBKB: liveins: $x10
; RV64ZBB_OR_RV64ZBKB-NEXT: {{ $}}
; RV64ZBB_OR_RV64ZBKB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; RV64ZBB_OR_RV64ZBKB-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s64) = G_ASSERT_ZEXT [[COPY]], 32
; RV64ZBB_OR_RV64ZBKB-NEXT: [[BSWAP:%[0-9]+]]:_(s64) = G_BSWAP [[ASSERT_ZEXT]]
; RV64ZBB_OR_RV64ZBKB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
; RV64ZBB_OR_RV64ZBKB-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[BSWAP]], [[C]](s64)
; RV64ZBB_OR_RV64ZBKB-NEXT: $x10 = COPY [[LSHR]](s64)
; RV64ZBB_OR_RV64ZBKB-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
%1:_(s64) = G_ASSERT_ZEXT %0, 32
%2:_(s32) = G_TRUNC %1(s64)
Expand Down Expand Up @@ -132,13 +134,13 @@ body: |
; RV64I-NEXT: $x10 = COPY [[OR6]](s64)
; RV64I-NEXT: PseudoRET implicit $x10
;
; RV64ZBB-LABEL: name: bswap_i64
; RV64ZBB: liveins: $x10
; RV64ZBB-NEXT: {{ $}}
; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; RV64ZBB-NEXT: [[BSWAP:%[0-9]+]]:_(s64) = G_BSWAP [[COPY]]
; RV64ZBB-NEXT: $x10 = COPY [[BSWAP]](s64)
; RV64ZBB-NEXT: PseudoRET implicit $x10
; RV64ZBB_OR_RV64ZBKB-LABEL: name: bswap_i64
; RV64ZBB_OR_RV64ZBKB: liveins: $x10
; RV64ZBB_OR_RV64ZBKB-NEXT: {{ $}}
; RV64ZBB_OR_RV64ZBKB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; RV64ZBB_OR_RV64ZBKB-NEXT: [[BSWAP:%[0-9]+]]:_(s64) = G_BSWAP [[COPY]]
; RV64ZBB_OR_RV64ZBKB-NEXT: $x10 = COPY [[BSWAP]](s64)
; RV64ZBB_OR_RV64ZBKB-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
%1:_(s64) = G_BSWAP %0
$x10 = COPY %1(s64)
Expand Down