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[SPARC] Prefer RDPC over CALL to implement GETPCX for 64-bit target #77196

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Merged
merged 4 commits into from
Jan 14, 2024
Merged

[SPARC] Prefer RDPC over CALL to implement GETPCX for 64-bit target #77196

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fe29e4f
[𝘀𝗽𝗿] initial version
koachan Jan 6, 2024
0c85312
Implement suggestions & clarify comment on RDPC emission
koachan Jan 10, 2024
f483082
Add nounwind to test cases
koachan Jan 14, 2024
811e1de
Fixup load pointer type in testcase
koachan Jan 14, 2024
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18 changes: 14 additions & 4 deletions llvm/lib/Target/Sparc/Sparc.td
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Original file line number Diff line number Diff line change
Expand Up @@ -62,6 +62,13 @@ def UsePopc : SubtargetFeature<"popc", "UsePopc", "true",
def FeatureSoftFloat : SubtargetFeature<"soft-float", "UseSoftFloat", "true",
"Use software emulation for floating point">;

//===----------------------------------------------------------------------===//
// SPARC Subtarget tuning features.
//

def TuneSlowRDPC : SubtargetFeature<"slow-rdpc", "HasSlowRDPC", "true",
"rd %pc, %XX is slow", [FeatureV9]>;

//==== Features added predmoninantly for LEON subtarget support
include "LeonFeatures.td"

Expand Down Expand Up @@ -89,8 +96,9 @@ def SparcAsmParserVariant : AsmParserVariant {
// SPARC processors supported.
//===----------------------------------------------------------------------===//

class Proc<string Name, list<SubtargetFeature> Features>
: Processor<Name, NoItineraries, Features>;
class Proc<string Name, list<SubtargetFeature> Features,
list<SubtargetFeature> TuneFeatures = []>
: Processor<Name, NoItineraries, Features, TuneFeatures>;

def : Proc<"generic", []>;
def : Proc<"v7", [FeatureSoftMulDiv, FeatureNoFSMULD]>;
Expand Down Expand Up @@ -118,9 +126,11 @@ def : Proc<"ma2480", [FeatureLeon, LeonCASA]>;
def : Proc<"ma2485", [FeatureLeon, LeonCASA]>;
def : Proc<"ma2x8x", [FeatureLeon, LeonCASA]>;
def : Proc<"v9", [FeatureV9]>;
def : Proc<"ultrasparc", [FeatureV9, FeatureV8Deprecated, FeatureVIS]>;
def : Proc<"ultrasparc", [FeatureV9, FeatureV8Deprecated, FeatureVIS],
[TuneSlowRDPC]>;
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Why is it in TuneFeatures? Sparc doesn't seem to support -mtune.

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-mtune enablement is at PR #77195.
clang already accepts, recognises, and passes the flag on to the backend, it's just the backend haven't made any use of the provided info yet.

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@s-barannikov s-barannikov Jan 8, 2024 •
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I see. IIUC -mtune is translated into -tune-cpu llc option. If so, the test should use this option.

def : Proc<"ultrasparc3", [FeatureV9, FeatureV8Deprecated, FeatureVIS,
FeatureVIS2]>;
FeatureVIS2],
[TuneSlowRDPC]>;
def : Proc<"niagara", [FeatureV9, FeatureV8Deprecated, FeatureVIS,
FeatureVIS2]>;
def : Proc<"niagara2", [FeatureV9, FeatureV8Deprecated, UsePopc,
Expand Down
25 changes: 22 additions & 3 deletions llvm/lib/Target/Sparc/SparcAsmPrinter.cpp
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Expand Up @@ -13,6 +13,7 @@

#include "MCTargetDesc/SparcInstPrinter.h"
#include "MCTargetDesc/SparcMCExpr.h"
#include "MCTargetDesc/SparcMCTargetDesc.h"
#include "MCTargetDesc/SparcTargetStreamer.h"
#include "Sparc.h"
#include "SparcInstrInfo.h"
Expand Down Expand Up @@ -111,6 +112,15 @@ static void EmitCall(MCStreamer &OutStreamer,
OutStreamer.emitInstruction(CallInst, STI);
}

static void EmitRDPC(MCStreamer &OutStreamer, MCOperand &RD,
const MCSubtargetInfo &STI) {
MCInst RDPCInst;
RDPCInst.setOpcode(SP::RDASR);
RDPCInst.addOperand(RD);
RDPCInst.addOperand(MCOperand::createReg(SP::ASR5));
OutStreamer.emitInstruction(RDPCInst, STI);
}

static void EmitSETHI(MCStreamer &OutStreamer,
MCOperand &Imm, MCOperand &RD,
const MCSubtargetInfo &STI)
Expand Down Expand Up @@ -226,16 +236,25 @@ void SparcAsmPrinter::LowerGETPCXAndEmitMCInsts(const MachineInstr *MI,
MCOperand RegO7 = MCOperand::createReg(SP::O7);

// <StartLabel>:
// call <EndLabel>
// <GET-PC> // This will be either `call <EndLabel>` or `rd %pc, %o7`.
// <SethiLabel>:
// sethi %hi(_GLOBAL_OFFSET_TABLE_+(<SethiLabel>-<StartLabel>)), <MO>
// <EndLabel>:
// or <MO>, %lo(_GLOBAL_OFFSET_TABLE_+(<EndLabel>-<StartLabel>))), <MO>
// add <MO>, %o7, <MO>

OutStreamer->emitLabel(StartLabel);
MCOperand Callee = createPCXCallOP(EndLabel, OutContext);
EmitCall(*OutStreamer, Callee, STI);
if (!STI.getTargetTriple().isSPARC64() ||
STI.hasFeature(Sparc::TuneSlowRDPC)) {
MCOperand Callee = createPCXCallOP(EndLabel, OutContext);
EmitCall(*OutStreamer, Callee, STI);
} else {
// TODO find out whether it is possible to store PC
// in other registers, to enable leaf function optimization.
// (On the other hand, approx. over 97.8% of GETPCXes happen
// in non-leaf functions, so would this be worth the effort?)
EmitRDPC(*OutStreamer, RegO7, STI);
}
OutStreamer->emitLabel(SethiLabel);
MCOperand hiImm = createPCXRelExprOp(SparcMCExpr::VK_Sparc_PC22,
GOTLabel, StartLabel, SethiLabel,
Expand Down
51 changes: 51 additions & 0 deletions llvm/test/CodeGen/SPARC/getpcx-call.ll
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@@ -0,0 +1,51 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -relocation-model=pic -mtriple=sparc | FileCheck --check-prefix=SPARC %s
; RUN: llc < %s -relocation-model=pic -mtriple=sparcv9 | FileCheck --check-prefix=SPARC64 %s

;; SPARC32 and SPARC64 for classic UltraSPARCs implement GETPCX
;; with a fake `call`.
;; All other SPARC64 targets implement it with `rd %pc, %o7`.
;; Need to do the tests in separate files because apparently `tune-cpu`
;; attribute applies to the entire file at once.

@value = external global i32

define i32 @testCall() nounwind #0 {
; SPARC-LABEL: testCall:
; SPARC: ! %bb.0:
; SPARC-NEXT: save %sp, -96, %sp
; SPARC-NEXT: .Ltmp0:
; SPARC-NEXT: call .Ltmp1
; SPARC-NEXT: .Ltmp2:
; SPARC-NEXT: sethi %hi(_GLOBAL_OFFSET_TABLE_+(.Ltmp2-.Ltmp0)), %i0
; SPARC-NEXT: .Ltmp1:
; SPARC-NEXT: or %i0, %lo(_GLOBAL_OFFSET_TABLE_+(.Ltmp1-.Ltmp0)), %i0
; SPARC-NEXT: add %i0, %o7, %i0
; SPARC-NEXT: sethi %hi(value), %i1
; SPARC-NEXT: add %i1, %lo(value), %i1
; SPARC-NEXT: ld [%i0+%i1], %i0
; SPARC-NEXT: ld [%i0], %i0
; SPARC-NEXT: ret
; SPARC-NEXT: restore
;
; SPARC64-LABEL: testCall:
; SPARC64: ! %bb.0:
; SPARC64-NEXT: save %sp, -128, %sp
; SPARC64-NEXT: .Ltmp0:
; SPARC64-NEXT: call .Ltmp1
; SPARC64-NEXT: .Ltmp2:
; SPARC64-NEXT: sethi %hi(_GLOBAL_OFFSET_TABLE_+(.Ltmp2-.Ltmp0)), %i0
; SPARC64-NEXT: .Ltmp1:
; SPARC64-NEXT: or %i0, %lo(_GLOBAL_OFFSET_TABLE_+(.Ltmp1-.Ltmp0)), %i0
; SPARC64-NEXT: add %i0, %o7, %i0
; SPARC64-NEXT: sethi %hi(value), %i1
; SPARC64-NEXT: add %i1, %lo(value), %i1
; SPARC64-NEXT: ldx [%i0+%i1], %i0
; SPARC64-NEXT: ld [%i0], %i0
; SPARC64-NEXT: ret
; SPARC64-NEXT: restore
%1 = load i32, ptr @value
ret i32 %1
}

attributes #0 = { "tune-cpu"="ultrasparc" }
51 changes: 51 additions & 0 deletions llvm/test/CodeGen/SPARC/getpcx-rdpc.ll
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@@ -0,0 +1,51 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -relocation-model=pic -mtriple=sparc | FileCheck --check-prefix=SPARC %s
; RUN: llc < %s -relocation-model=pic -mtriple=sparcv9 | FileCheck --check-prefix=SPARC64 %s

;; SPARC32 and SPARC64 for classic UltraSPARCs implement GETPCX
;; with a fake `call`.
;; All other SPARC64 targets implement it with `rd %pc, %o7`.
;; Need to do the tests in separate files because apparently `tune-cpu`
;; attribute applies to the entire file at once.

@value = external global i32

define i32 @testRdpc() nounwind #0 {
; SPARC-LABEL: testRdpc:
; SPARC: ! %bb.0:
; SPARC-NEXT: save %sp, -96, %sp
; SPARC-NEXT: .Ltmp0:
; SPARC-NEXT: call .Ltmp1
; SPARC-NEXT: .Ltmp2:
; SPARC-NEXT: sethi %hi(_GLOBAL_OFFSET_TABLE_+(.Ltmp2-.Ltmp0)), %i0
; SPARC-NEXT: .Ltmp1:
; SPARC-NEXT: or %i0, %lo(_GLOBAL_OFFSET_TABLE_+(.Ltmp1-.Ltmp0)), %i0
; SPARC-NEXT: add %i0, %o7, %i0
; SPARC-NEXT: sethi %hi(value), %i1
; SPARC-NEXT: add %i1, %lo(value), %i1
; SPARC-NEXT: ld [%i0+%i1], %i0
; SPARC-NEXT: ld [%i0], %i0
; SPARC-NEXT: ret
; SPARC-NEXT: restore
;
; SPARC64-LABEL: testRdpc:
; SPARC64: ! %bb.0:
; SPARC64-NEXT: save %sp, -128, %sp
; SPARC64-NEXT: .Ltmp0:
; SPARC64-NEXT: rd %pc, %o7
; SPARC64-NEXT: .Ltmp2:
; SPARC64-NEXT: sethi %hi(_GLOBAL_OFFSET_TABLE_+(.Ltmp2-.Ltmp0)), %i0
; SPARC64-NEXT: .Ltmp1:
; SPARC64-NEXT: or %i0, %lo(_GLOBAL_OFFSET_TABLE_+(.Ltmp1-.Ltmp0)), %i0
; SPARC64-NEXT: add %i0, %o7, %i0
; SPARC64-NEXT: sethi %hi(value), %i1
; SPARC64-NEXT: add %i1, %lo(value), %i1
; SPARC64-NEXT: ldx [%i0+%i1], %i0
; SPARC64-NEXT: ld [%i0], %i0
; SPARC64-NEXT: ret
; SPARC64-NEXT: restore
%1 = load i32, ptr @value
ret i32 %1
}

attributes #0 = { "tune-cpu"="niagara" }