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[Legalizer] Soften EXTRACT_ELEMENT on ppcf128 #77412

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Merged
merged 3 commits into from
Apr 9, 2024
Merged

[Legalizer] Soften EXTRACT_ELEMENT on ppcf128 #77412

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1bdce09
[Legalizer] Soften EXTRACT_ELEMENT on ppcf128
ecnelises Jan 9, 2024
83cf5d1
Use bitcast
ecnelises Apr 4, 2024
caafabc
Change formatting
ecnelises Apr 5, 2024
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11 changes: 10 additions & 1 deletion llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -60,7 +60,7 @@ void DAGTypeLegalizer::SoftenFloatResult(SDNode *N, unsigned ResNo) {
#endif
report_fatal_error("Do not know how to soften the result of this "
"operator!");

case ISD::EXTRACT_ELEMENT: R = SoftenFloatRes_EXTRACT_ELEMENT(N); break;
case ISD::ARITH_FENCE: R = SoftenFloatRes_ARITH_FENCE(N); break;
case ISD::MERGE_VALUES:R = SoftenFloatRes_MERGE_VALUES(N, ResNo); break;
case ISD::BITCAST: R = SoftenFloatRes_BITCAST(N); break;
Expand Down Expand Up @@ -262,6 +262,15 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_ConstantFP(SDNode *N) {
}
}

SDValue DAGTypeLegalizer::SoftenFloatRes_EXTRACT_ELEMENT(SDNode *N) {
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In the test case, this is a float operand, not the result? Why does ppcf128 require softening on ppc?

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It's something like

        t10: i64 = build_pair t8, t6
        t9: i64 = build_pair t4, t2
      t11: i128 = build_pair t10, t9
    t12: ppcf128 = bitcast t11
  t14: f64 = extract_element t12, Constant:i32<1>
t15: i64 = bitcast t14

ppc_fp128 is operand, but result is also a float value which needs soften. Only ppc_fp128 supports extract_element (it consists of two f64s) and result of extracting from ppc_fp128 is f64.

Calling the type ppc_fp128 is because only PPC uses the format, but PPC also does not support it in hardware instruction level, it's always soft.

SDValue Src = N->getOperand(0);
assert(Src.getValueType() == MVT::ppcf128 &&
"In floats only ppcf128 can be extracted by element!");
return DAG.getNode(ISD::EXTRACT_ELEMENT, SDLoc(N),
N->getValueType(0).changeTypeToInteger(),
DAG.getBitcast(MVT::i128, Src), N->getOperand(1));
}

SDValue DAGTypeLegalizer::SoftenFloatRes_EXTRACT_VECTOR_ELT(SDNode *N, unsigned ResNo) {
SDValue NewOp = BitConvertVectorToIntegerVector(N->getOperand(0));
return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N),
Expand Down
1 change: 1 addition & 0 deletions llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
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Expand Up @@ -530,6 +530,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
SDValue SoftenFloatRes_BITCAST(SDNode *N);
SDValue SoftenFloatRes_BUILD_PAIR(SDNode *N);
SDValue SoftenFloatRes_ConstantFP(SDNode *N);
SDValue SoftenFloatRes_EXTRACT_ELEMENT(SDNode *N);
SDValue SoftenFloatRes_EXTRACT_VECTOR_ELT(SDNode *N, unsigned ResNo);
SDValue SoftenFloatRes_FABS(SDNode *N);
SDValue SoftenFloatRes_FMINNUM(SDNode *N);
Expand Down
60 changes: 60 additions & 0 deletions llvm/test/CodeGen/PowerPC/ppcsoftops.ll
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Expand Up @@ -312,8 +312,68 @@ define dso_local zeroext i32 @func(double noundef %0, double noundef %1) #0 {
ret i32 %9
}

; To check ppc_fp128 soften without crash
define zeroext i1 @ppcf128_soften(ppc_fp128 %a) #0 {
; PPC-LABEL: ppcf128_soften:
; PPC: # %bb.0: # %entry
; PPC-NEXT: stwu 1, -16(1)
; PPC-NEXT: stw 5, 8(1) # 4-byte Folded Spill
; PPC-NEXT: mr 5, 4
; PPC-NEXT: lwz 4, 8(1) # 4-byte Folded Reload
; PPC-NEXT: stw 5, 12(1) # 4-byte Folded Spill
; PPC-NEXT: mr 5, 3
; PPC-NEXT: lwz 3, 12(1) # 4-byte Folded Reload
; PPC-NEXT: # kill: def $r4 killed $r3
; PPC-NEXT: # kill: def $r4 killed $r5
; PPC-NEXT: xoris 4, 5, 65520
; PPC-NEXT: or 4, 3, 4
; PPC-NEXT: cntlzw 4, 4
; PPC-NEXT: clrlwi 5, 5, 1
; PPC-NEXT: or 3, 3, 5
; PPC-NEXT: cntlzw 3, 3
; PPC-NEXT: or 3, 3, 4
; PPC-NEXT: srwi 3, 3, 5
; PPC-NEXT: addi 1, 1, 16
; PPC-NEXT: blr
;
; PPC64-LABEL: ppcf128_soften:
; PPC64: # %bb.0: # %entry
; PPC64-NEXT: li 4, 4095
; PPC64-NEXT: rldic 4, 4, 52, 0
; PPC64-NEXT: cmpld 7, 3, 4
; PPC64-NEXT: mfcr 4 # cr7
; PPC64-NEXT: rlwinm 4, 4, 31, 31, 31
; PPC64-NEXT: clrldi 3, 3, 1
; PPC64-NEXT: cmpldi 7, 3, 0
; PPC64-NEXT: mfcr 3 # cr7
; PPC64-NEXT: rlwinm 3, 3, 31, 31, 31
; PPC64-NEXT: or 4, 3, 4
; PPC64-NEXT: # implicit-def: $x3
; PPC64-NEXT: mr 3, 4
; PPC64-NEXT: clrldi 3, 3, 32
; PPC64-NEXT: blr
;
; PPC64LE-LABEL: ppcf128_soften:
; PPC64LE: # %bb.0: # %entry
; PPC64LE-NEXT: li 3, 4095
; PPC64LE-NEXT: rldic 3, 3, 52, 0
; PPC64LE-NEXT: cmpd 4, 3
; PPC64LE-NEXT: crmove 21, 2
; PPC64LE-NEXT: clrldi. 3, 4, 1
; PPC64LE-NEXT: crmove 20, 2
; PPC64LE-NEXT: cror 20, 20, 21
; PPC64LE-NEXT: li 4, 0
; PPC64LE-NEXT: li 3, 1
; PPC64LE-NEXT: isel 3, 3, 4, 20
; PPC64LE-NEXT: blr
entry:
%fpclass = tail call i1 @llvm.is.fpclass.ppcf128(ppc_fp128 %a, i32 100)
ret i1 %fpclass
}

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare double @llvm.fmuladd.f64(double, double, double) #1
declare i1 @llvm.is.fpclass.ppcf128(ppc_fp128, i32 immarg) #1

attributes #0 = {"use-soft-float"="true" nounwind }
attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }