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[SelectionDAG] Add and use SDNode::getAsAPIntVal() helper #77455

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Jan 9, 2024
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[SelectionDAG] Add and use SDNode::getAsAPIntVal() helper #77455

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799c67b
[SelectionDAG] Add and use SDNode::getAsAPIntVal() helper
asb Jan 2, 2024
42f4114
Remove extraneous parens in X86ISelLowering change
asb Jan 9, 2024
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7 changes: 7 additions & 0 deletions llvm/include/llvm/CodeGen/SelectionDAGNodes.h
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Expand Up @@ -932,6 +932,9 @@ END_TWO_BYTE_PACK()
/// Helper method returns the APInt of a ConstantSDNode operand.
inline const APInt &getConstantOperandAPInt(unsigned Num) const;

/// Helper method returns the APInt value of a ConstantSDNode.
inline const APInt &getAsAPIntVal() const;

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Why not directly put the definition here?

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The definition of ConstantSDNode doesn't come until later in the file, and this matches the approach used by the neighbouring getters.

const SDValue &getOperand(unsigned Num) const {
assert(Num < NumOperands && "Invalid child # of SDNode!");
return OperandList[Num];
Expand Down Expand Up @@ -1649,6 +1652,10 @@ const APInt &SDNode::getConstantOperandAPInt(unsigned Num) const {
return cast<ConstantSDNode>(getOperand(Num))->getAPIntValue();
}

const APInt &SDNode::getAsAPIntVal() const {
return cast<ConstantSDNode>(this)->getAPIntValue();
}

class ConstantFPSDNode : public SDNode {
friend class SelectionDAG;

Expand Down
18 changes: 9 additions & 9 deletions llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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Expand Up @@ -4380,7 +4380,7 @@ SDValue DAGCombiner::visitMUL(SDNode *N) {
} else {
N1IsConst = isa<ConstantSDNode>(N1);
if (N1IsConst) {
ConstValue1 = cast<ConstantSDNode>(N1)->getAPIntValue();
ConstValue1 = N1->getAsAPIntVal();
N1IsOpaqueConst = cast<ConstantSDNode>(N1)->isOpaque();
}
}
Expand Down Expand Up @@ -12087,8 +12087,8 @@ SDValue DAGCombiner::foldVSelectOfConstants(SDNode *N) {
if (N1Elt.getValueType() != N2Elt.getValueType())
continue;

const APInt &C1 = cast<ConstantSDNode>(N1Elt)->getAPIntValue();
const APInt &C2 = cast<ConstantSDNode>(N2Elt)->getAPIntValue();
const APInt &C1 = N1Elt->getAsAPIntVal();
const APInt &C2 = N2Elt->getAsAPIntVal();
if (C1 != C2 + 1)
AllAddOne = false;
if (C1 != C2 - 1)
Expand Down Expand Up @@ -12764,7 +12764,7 @@ static SDValue tryToFoldExtendOfConstant(SDNode *N, const TargetLowering &TLI,
SDLoc DL(Op);
// Get the constant value and if needed trunc it to the size of the type.
// Nodes like build_vector might have constants wider than the scalar type.
APInt C = cast<ConstantSDNode>(Op)->getAPIntValue().zextOrTrunc(EVTBits);
APInt C = Op->getAsAPIntVal().zextOrTrunc(EVTBits);
if (Opcode == ISD::SIGN_EXTEND || Opcode == ISD::SIGN_EXTEND_VECTOR_INREG)
Elts.push_back(DAG.getConstant(C.sext(VTBits), DL, SVT));
else
Expand Down Expand Up @@ -17942,10 +17942,10 @@ SDValue DAGCombiner::rebuildSetCC(SDValue N) {
SDValue AndOp1 = Op0.getOperand(1);

if (AndOp1.getOpcode() == ISD::Constant) {
const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue();
const APInt &AndConst = AndOp1->getAsAPIntVal();

if (AndConst.isPowerOf2() &&
cast<ConstantSDNode>(Op1)->getAPIntValue() == AndConst.logBase2()) {
Op1->getAsAPIntVal() == AndConst.logBase2()) {
SDLoc DL(N);
return DAG.getSetCC(DL, getSetCCResultType(Op0.getValueType()),
Op0, DAG.getConstant(0, DL, Op0.getValueType()),
Expand Down Expand Up @@ -18266,7 +18266,7 @@ bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) {

auto *CN = cast<ConstantSDNode>(OtherUses[i]->getOperand(OffsetIdx));
const APInt &Offset0 = CN->getAPIntValue();
const APInt &Offset1 = cast<ConstantSDNode>(Offset)->getAPIntValue();
const APInt &Offset1 = Offset->getAsAPIntVal();
int X0 = (OtherUses[i]->getOpcode() == ISD::SUB && OffsetIdx == 1) ? -1 : 1;
int Y0 = (OtherUses[i]->getOpcode() == ISD::SUB && OffsetIdx == 0) ? -1 : 1;
int X1 = (AM == ISD::PRE_DEC && !Swapped) ? -1 : 1;
Expand Down Expand Up @@ -19573,7 +19573,7 @@ SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) {
// Find the type to narrow it the load / op / store to.
SDValue N1 = Value.getOperand(1);
unsigned BitWidth = N1.getValueSizeInBits();
APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue();
APInt Imm = N1->getAsAPIntVal();
if (Opc == ISD::AND)
Imm ^= APInt::getAllOnes(BitWidth);
if (Imm == 0 || Imm.isAllOnes())
Expand Down Expand Up @@ -26543,7 +26543,7 @@ SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) {

APInt Bits;
if (isa<ConstantSDNode>(Elt))
Bits = cast<ConstantSDNode>(Elt)->getAPIntValue();
Bits = Elt->getAsAPIntVal();
else if (isa<ConstantFPSDNode>(Elt))
Bits = cast<ConstantFPSDNode>(Elt)->getValueAPF().bitcastToAPInt();
else
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
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Expand Up @@ -1854,7 +1854,7 @@ void DAGTypeLegalizer::SplitVecRes_STEP_VECTOR(SDNode *N, SDValue &Lo,

// Hi = Lo + (EltCnt * Step)
EVT EltVT = Step.getValueType();
APInt StepVal = cast<ConstantSDNode>(Step)->getAPIntValue();
APInt StepVal = Step->getAsAPIntVal();
SDValue StartOfHi =
DAG.getVScale(dl, EltVT, StepVal * LoVT.getVectorMinNumElements());
StartOfHi = DAG.getSExtOrTrunc(StartOfHi, dl, HiVT.getVectorElementType());
Expand Down
12 changes: 6 additions & 6 deletions llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
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Expand Up @@ -327,7 +327,7 @@ bool ISD::isVectorShrinkable(const SDNode *N, unsigned NewEltSize,
if (!isa<ConstantSDNode>(Op))
return false;

APInt C = cast<ConstantSDNode>(Op)->getAPIntValue().trunc(EltSize);
APInt C = Op->getAsAPIntVal().trunc(EltSize);
if (Signed && C.trunc(NewEltSize).sext(EltSize) != C)
return false;
if (!Signed && C.trunc(NewEltSize).zext(EltSize) != C)
Expand Down Expand Up @@ -7201,7 +7201,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
cast<ConstantSDNode>(N3)->getZExtValue()) <=
VT.getVectorMinNumElements()) &&
"Insert subvector overflow!");
assert(cast<ConstantSDNode>(N3)->getAPIntValue().getBitWidth() ==
assert(N3->getAsAPIntVal().getBitWidth() ==
TLI->getVectorIdxTy(getDataLayout()).getFixedSizeInBits() &&
"Constant index for INSERT_SUBVECTOR has an invalid size");

Expand Down Expand Up @@ -9305,7 +9305,7 @@ SDValue SelectionDAG::getGatherVP(SDVTList VTs, EVT VT, const SDLoc &dl,
N->getValueType(0).getVectorElementCount()) &&
"Vector width mismatch between index and data");
assert(isa<ConstantSDNode>(N->getScale()) &&
cast<ConstantSDNode>(N->getScale())->getAPIntValue().isPowerOf2() &&
N->getScale()->getAsAPIntVal().isPowerOf2() &&
"Scale should be a constant power of 2");

CSEMap.InsertNode(N, IP);
Expand Down Expand Up @@ -9349,7 +9349,7 @@ SDValue SelectionDAG::getScatterVP(SDVTList VTs, EVT VT, const SDLoc &dl,
N->getValue().getValueType().getVectorElementCount()) &&
"Vector width mismatch between index and data");
assert(isa<ConstantSDNode>(N->getScale()) &&
cast<ConstantSDNode>(N->getScale())->getAPIntValue().isPowerOf2() &&
N->getScale()->getAsAPIntVal().isPowerOf2() &&
"Scale should be a constant power of 2");

CSEMap.InsertNode(N, IP);
Expand Down Expand Up @@ -9491,7 +9491,7 @@ SDValue SelectionDAG::getMaskedGather(SDVTList VTs, EVT MemVT, const SDLoc &dl,
N->getValueType(0).getVectorElementCount()) &&
"Vector width mismatch between index and data");
assert(isa<ConstantSDNode>(N->getScale()) &&
cast<ConstantSDNode>(N->getScale())->getAPIntValue().isPowerOf2() &&
N->getScale()->getAsAPIntVal().isPowerOf2() &&
"Scale should be a constant power of 2");

CSEMap.InsertNode(N, IP);
Expand Down Expand Up @@ -9537,7 +9537,7 @@ SDValue SelectionDAG::getMaskedScatter(SDVTList VTs, EVT MemVT, const SDLoc &dl,
N->getValue().getValueType().getVectorElementCount()) &&
"Vector width mismatch between index and data");
assert(isa<ConstantSDNode>(N->getScale()) &&
cast<ConstantSDNode>(N->getScale())->getAPIntValue().isPowerOf2() &&
N->getScale()->getAsAPIntVal().isPowerOf2() &&
"Scale should be a constant power of 2");

CSEMap.InsertNode(N, IP);
Expand Down
5 changes: 2 additions & 3 deletions llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
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Expand Up @@ -1108,7 +1108,7 @@ bool TargetLowering::SimplifyDemandedBits(

if (Op.getOpcode() == ISD::Constant) {
// We know all of the bits for a constant!
Known = KnownBits::makeConstant(cast<ConstantSDNode>(Op)->getAPIntValue());
Known = KnownBits::makeConstant(Op->getAsAPIntVal());
return false;
}

Expand Down Expand Up @@ -6350,8 +6350,7 @@ SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG,
LeadingZeros = DAG.computeKnownBits(N0).countMinLeadingZeros();
// UnsignedDivisionByConstantInfo doesn't work correctly if leading zeros in
// the dividend exceeds the leading zeros for the divisor.
LeadingZeros = std::min(
LeadingZeros, cast<ConstantSDNode>(N1)->getAPIntValue().countl_zero());
LeadingZeros = std::min(LeadingZeros, N1->getAsAPIntVal().countl_zero());
}

bool UseNPQ = false, UsePreShift = false, UsePostShift = false;
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
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Expand Up @@ -2483,7 +2483,7 @@ void AMDGPUDAGToDAGISel::SelectDSAppendConsume(SDNode *N, unsigned IntrID) {
SDValue PtrBase = Ptr.getOperand(0);
SDValue PtrOffset = Ptr.getOperand(1);

const APInt &OffsetVal = cast<ConstantSDNode>(PtrOffset)->getAPIntValue();
const APInt &OffsetVal = PtrOffset->getAsAPIntVal();
if (isDSOffsetLegal(PtrBase, OffsetVal.getZExtValue())) {
N = glueCopyToM0(N, PtrBase);
Offset = CurDAG->getTargetConstant(OffsetVal, SDLoc(), MVT::i32);
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
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Expand Up @@ -2297,7 +2297,7 @@ SDValue NVPTXTargetLowering::LowerBUILD_VECTOR(SDValue Op,
if (VT == MVT::v2f16 || VT == MVT::v2bf16)
Value = cast<ConstantFPSDNode>(Operand)->getValueAPF().bitcastToAPInt();
else if (VT == MVT::v2i16 || VT == MVT::v4i8)
Value = cast<ConstantSDNode>(Operand)->getAPIntValue();
Value = Operand->getAsAPIntVal();
else
llvm_unreachable("Unsupported type");
// i8 values are carried around as i16, so we need to zero out upper bits,
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/PowerPC/PPCISelLowering.cpp
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Expand Up @@ -16241,7 +16241,7 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
// Since we are doing this pre-legalize, the RHS can be a constant of
// arbitrary bitwidth which may cause issues when trying to get the value
// from the underlying APInt.
auto RHSAPInt = cast<ConstantSDNode>(RHS)->getAPIntValue();
auto RHSAPInt = RHS->getAsAPIntVal();
if (!RHSAPInt.isIntN(64))
break;

Expand Down
7 changes: 3 additions & 4 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Expand Up @@ -7024,8 +7024,7 @@ foldBinOpIntoSelectIfProfitable(SDNode *BO, SelectionDAG &DAG,
if (!NewConstOp)
return SDValue();

const APInt &NewConstAPInt =
cast<ConstantSDNode>(NewConstOp)->getAPIntValue();
const APInt &NewConstAPInt = NewConstOp->getAsAPIntVal();
if (!NewConstAPInt.isZero() && !NewConstAPInt.isAllOnes())
return SDValue();

Expand Down Expand Up @@ -7155,8 +7154,8 @@ SDValue RISCVTargetLowering::lowerSELECT(SDValue Op, SelectionDAG &DAG) const {
// is SETGE/SETLE to avoid an XORI.
if (isa<ConstantSDNode>(TrueV) && isa<ConstantSDNode>(FalseV) &&
CCVal == ISD::SETLT) {
const APInt &TrueVal = cast<ConstantSDNode>(TrueV)->getAPIntValue();
const APInt &FalseVal = cast<ConstantSDNode>(FalseV)->getAPIntValue();
const APInt &TrueVal = TrueV->getAsAPIntVal();
const APInt &FalseVal = FalseV->getAsAPIntVal();
if (TrueVal - 1 == FalseVal)
return DAG.getNode(ISD::ADD, DL, VT, CondV, FalseV);
if (TrueVal + 1 == FalseVal)
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
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Expand Up @@ -1649,7 +1649,7 @@ void SystemZDAGToDAGISel::Select(SDNode *Node) {
}
}
if (Node->getValueType(0) == MVT::i128) {
const APInt &Val = cast<ConstantSDNode>(Node)->getAPIntValue();
const APInt &Val = Node->getAsAPIntVal();
SystemZVectorConstantInfo VCI(Val);
if (VCI.isVectorConstantLegal(*Subtarget)) {
loadVectorConstant(VCI, Node);
Expand Down
6 changes: 3 additions & 3 deletions llvm/lib/Target/X86/X86ISelLowering.cpp
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Expand Up @@ -22551,7 +22551,7 @@ static SDValue EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
// FIXME: Do this for non-constant compares for constant on LHS?
if (CmpVT == MVT::i64 && isa<ConstantSDNode>(Op1) && !isX86CCSigned(X86CC) &&
Op0.hasOneUse() && // Hacky way to not break CSE opportunities with sub.
cast<ConstantSDNode>(Op1)->getAPIntValue().getActiveBits() <= 32 &&
Op1->getAsAPIntVal().getActiveBits() <= 32 &&
DAG.MaskedValueIsZero(Op0, APInt::getHighBitsSet(64, 32))) {
CmpVT = MVT::i32;
Op0 = DAG.getNode(ISD::TRUNCATE, dl, CmpVT, Op0);
Expand Down Expand Up @@ -47031,8 +47031,8 @@ static SDValue combineShiftRightArithmetic(SDNode *N, SelectionDAG &DAG,

SDValue N00 = N0.getOperand(0);
SDValue N01 = N0.getOperand(1);
APInt ShlConst = (cast<ConstantSDNode>(N01))->getAPIntValue();
APInt SarConst = (cast<ConstantSDNode>(N1))->getAPIntValue();
APInt ShlConst = N01->getAsAPIntVal();
APInt SarConst = N1->getAsAPIntVal();
EVT CVT = N1.getValueType();

if (SarConst.isNegative())
Expand Down
2 changes: 1 addition & 1 deletion llvm/utils/TableGen/CodeGenDAGPatterns.cpp
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Expand Up @@ -1368,7 +1368,7 @@ std::string TreePredicateFn::getCodeToRunOnSDNode() const {
if (immCodeUsesAPFloat())
Result += "cast<ConstantFPSDNode>(Node)->getValueAPF();\n";
else if (immCodeUsesAPInt())
Result += "cast<ConstantSDNode>(Node)->getAPIntValue();\n";
Result += "Node->getAsAPIntVal();\n";
else
Result += "cast<ConstantSDNode>(Node)->getSExtValue();\n";
return Result + ImmCode;
Expand Down