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[RISCV] Reorder RISCVInstrInfoA.td NFC #77539

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Jan 10, 2024
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[RISCV] Reorder RISCVInstrInfoA.td NFC #77539

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130 changes: 67 additions & 63 deletions llvm/lib/Target/RISCV/RISCVInstrInfoA.td
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Original file line number Diff line number Diff line change
Expand Up @@ -157,7 +157,16 @@ defm : AMOPat<"atomic_load_min_32", "AMOMIN_W">;
defm : AMOPat<"atomic_load_umax_32", "AMOMAXU_W">;
defm : AMOPat<"atomic_load_umin_32", "AMOMINU_W">;

let Predicates = [HasStdExtA] in {
defm : AMOPat<"atomic_swap_64", "AMOSWAP_D", i64, [IsRV64]>;
defm : AMOPat<"atomic_load_add_64", "AMOADD_D", i64, [IsRV64]>;
defm : AMOPat<"atomic_load_and_64", "AMOAND_D", i64, [IsRV64]>;
defm : AMOPat<"atomic_load_or_64", "AMOOR_D", i64, [IsRV64]>;
defm : AMOPat<"atomic_load_xor_64", "AMOXOR_D", i64, [IsRV64]>;
defm : AMOPat<"atomic_load_max_64", "AMOMAX_D", i64, [IsRV64]>;
defm : AMOPat<"atomic_load_min_64", "AMOMIN_D", i64, [IsRV64]>;
defm : AMOPat<"atomic_load_umax_64", "AMOMAXU_D", i64, [IsRV64]>;
defm : AMOPat<"atomic_load_umin_64", "AMOMINU_D", i64, [IsRV64]>;


/// Pseudo AMOs

Expand All @@ -169,21 +178,6 @@ class PseudoAMO : Pseudo<(outs GPR:$res, GPR:$scratch),
let hasSideEffects = 0;
}

let Size = 20 in
def PseudoAtomicLoadNand32 : PseudoAMO;
// Ordering constants must be kept in sync with the AtomicOrdering enum in
// AtomicOrdering.h.
def : Pat<(XLenVT (atomic_load_nand_32_monotonic GPR:$addr, GPR:$incr)),
(PseudoAtomicLoadNand32 GPR:$addr, GPR:$incr, 2)>;
def : Pat<(XLenVT (atomic_load_nand_32_acquire GPR:$addr, GPR:$incr)),
(PseudoAtomicLoadNand32 GPR:$addr, GPR:$incr, 4)>;
def : Pat<(XLenVT (atomic_load_nand_32_release GPR:$addr, GPR:$incr)),
(PseudoAtomicLoadNand32 GPR:$addr, GPR:$incr, 5)>;
def : Pat<(XLenVT (atomic_load_nand_32_acq_rel GPR:$addr, GPR:$incr)),
(PseudoAtomicLoadNand32 GPR:$addr, GPR:$incr, 6)>;
def : Pat<(XLenVT (atomic_load_nand_32_seq_cst GPR:$addr, GPR:$incr)),
(PseudoAtomicLoadNand32 GPR:$addr, GPR:$incr, 7)>;

class PseudoMaskedAMO
: Pseudo<(outs GPR:$res, GPR:$scratch),
(ins GPR:$addr, GPR:$incr, GPR:$mask, ixlenimm:$ordering), []> {
Expand Down Expand Up @@ -224,6 +218,23 @@ class PseudoMaskedAMOMinMaxPat<Intrinsic intrin, Pseudo AMOInst>
(AMOInst GPR:$addr, GPR:$incr, GPR:$mask, GPR:$shiftamt,
timm:$ordering)>;

let Predicates = [HasStdExtA] in {

let Size = 20 in
def PseudoAtomicLoadNand32 : PseudoAMO;
// Ordering constants must be kept in sync with the AtomicOrdering enum in
// AtomicOrdering.h.
def : Pat<(XLenVT (atomic_load_nand_32_monotonic GPR:$addr, GPR:$incr)),
(PseudoAtomicLoadNand32 GPR:$addr, GPR:$incr, 2)>;
def : Pat<(XLenVT (atomic_load_nand_32_acquire GPR:$addr, GPR:$incr)),
(PseudoAtomicLoadNand32 GPR:$addr, GPR:$incr, 4)>;
def : Pat<(XLenVT (atomic_load_nand_32_release GPR:$addr, GPR:$incr)),
(PseudoAtomicLoadNand32 GPR:$addr, GPR:$incr, 5)>;
def : Pat<(XLenVT (atomic_load_nand_32_acq_rel GPR:$addr, GPR:$incr)),
(PseudoAtomicLoadNand32 GPR:$addr, GPR:$incr, 6)>;
def : Pat<(XLenVT (atomic_load_nand_32_seq_cst GPR:$addr, GPR:$incr)),
(PseudoAtomicLoadNand32 GPR:$addr, GPR:$incr, 7)>;

let Size = 28 in
def PseudoMaskedAtomicSwap32 : PseudoMaskedAMO;
def : PseudoMaskedAMOPat<int_riscv_masked_atomicrmw_xchg_i32,
Expand Down Expand Up @@ -256,6 +267,43 @@ let Size = 36 in
def PseudoMaskedAtomicLoadUMin32 : PseudoMaskedAMOUMinUMax;
def : PseudoMaskedAMOPat<int_riscv_masked_atomicrmw_umin_i32,
PseudoMaskedAtomicLoadUMin32>;
} // Predicates = [HasStdExtA]

let Predicates = [HasStdExtA, IsRV64] in {

let Size = 20 in
def PseudoAtomicLoadNand64 : PseudoAMO;
// Ordering constants must be kept in sync with the AtomicOrdering enum in
// AtomicOrdering.h.
def : Pat<(i64 (atomic_load_nand_64_monotonic GPR:$addr, GPR:$incr)),
(PseudoAtomicLoadNand64 GPR:$addr, GPR:$incr, 2)>;
def : Pat<(i64 (atomic_load_nand_64_acquire GPR:$addr, GPR:$incr)),
(PseudoAtomicLoadNand64 GPR:$addr, GPR:$incr, 4)>;
def : Pat<(i64 (atomic_load_nand_64_release GPR:$addr, GPR:$incr)),
(PseudoAtomicLoadNand64 GPR:$addr, GPR:$incr, 5)>;
def : Pat<(i64 (atomic_load_nand_64_acq_rel GPR:$addr, GPR:$incr)),
(PseudoAtomicLoadNand64 GPR:$addr, GPR:$incr, 6)>;
def : Pat<(i64 (atomic_load_nand_64_seq_cst GPR:$addr, GPR:$incr)),
(PseudoAtomicLoadNand64 GPR:$addr, GPR:$incr, 7)>;

def : PseudoMaskedAMOPat<int_riscv_masked_atomicrmw_xchg_i64,
PseudoMaskedAtomicSwap32>;
def : PseudoMaskedAMOPat<int_riscv_masked_atomicrmw_add_i64,
PseudoMaskedAtomicLoadAdd32>;
def : PseudoMaskedAMOPat<int_riscv_masked_atomicrmw_sub_i64,
PseudoMaskedAtomicLoadSub32>;
def : PseudoMaskedAMOPat<int_riscv_masked_atomicrmw_nand_i64,
PseudoMaskedAtomicLoadNand32>;
def : PseudoMaskedAMOMinMaxPat<int_riscv_masked_atomicrmw_max_i64,
PseudoMaskedAtomicLoadMax32>;
def : PseudoMaskedAMOMinMaxPat<int_riscv_masked_atomicrmw_min_i64,
PseudoMaskedAtomicLoadMin32>;
def : PseudoMaskedAMOPat<int_riscv_masked_atomicrmw_umax_i64,
PseudoMaskedAtomicLoadUMax32>;
def : PseudoMaskedAMOPat<int_riscv_masked_atomicrmw_umin_i64,
PseudoMaskedAtomicLoadUMin32>;
} // Predicates = [HasStdExtA, IsRV64]


/// Compare and exchange

Expand Down Expand Up @@ -285,6 +333,8 @@ multiclass PseudoCmpXchgPat<string Op, Pseudo CmpXchgInst,
(CmpXchgInst GPR:$addr, GPR:$cmp, GPR:$new, 7)>;
}

let Predicates = [HasStdExtA] in {

def PseudoCmpXchg32 : PseudoCmpXchg;
defm : PseudoCmpXchgPat<"atomic_cmp_swap_32", PseudoCmpXchg32>;

Expand All @@ -303,57 +353,10 @@ def : Pat<(int_riscv_masked_cmpxchg_i32
GPR:$addr, GPR:$cmpval, GPR:$newval, GPR:$mask, timm:$ordering),
(PseudoMaskedCmpXchg32
GPR:$addr, GPR:$cmpval, GPR:$newval, GPR:$mask, timm:$ordering)>;

} // Predicates = [HasStdExtA]

defm : AMOPat<"atomic_swap_64", "AMOSWAP_D", i64, [IsRV64]>;
defm : AMOPat<"atomic_load_add_64", "AMOADD_D", i64, [IsRV64]>;
defm : AMOPat<"atomic_load_and_64", "AMOAND_D", i64, [IsRV64]>;
defm : AMOPat<"atomic_load_or_64", "AMOOR_D", i64, [IsRV64]>;
defm : AMOPat<"atomic_load_xor_64", "AMOXOR_D", i64, [IsRV64]>;
defm : AMOPat<"atomic_load_max_64", "AMOMAX_D", i64, [IsRV64]>;
defm : AMOPat<"atomic_load_min_64", "AMOMIN_D", i64, [IsRV64]>;
defm : AMOPat<"atomic_load_umax_64", "AMOMAXU_D", i64, [IsRV64]>;
defm : AMOPat<"atomic_load_umin_64", "AMOMINU_D", i64, [IsRV64]>;

let Predicates = [HasStdExtA, IsRV64] in {

/// 64-bit pseudo AMOs

let Size = 20 in
def PseudoAtomicLoadNand64 : PseudoAMO;
// Ordering constants must be kept in sync with the AtomicOrdering enum in
// AtomicOrdering.h.
def : Pat<(i64 (atomic_load_nand_64_monotonic GPR:$addr, GPR:$incr)),
(PseudoAtomicLoadNand64 GPR:$addr, GPR:$incr, 2)>;
def : Pat<(i64 (atomic_load_nand_64_acquire GPR:$addr, GPR:$incr)),
(PseudoAtomicLoadNand64 GPR:$addr, GPR:$incr, 4)>;
def : Pat<(i64 (atomic_load_nand_64_release GPR:$addr, GPR:$incr)),
(PseudoAtomicLoadNand64 GPR:$addr, GPR:$incr, 5)>;
def : Pat<(i64 (atomic_load_nand_64_acq_rel GPR:$addr, GPR:$incr)),
(PseudoAtomicLoadNand64 GPR:$addr, GPR:$incr, 6)>;
def : Pat<(i64 (atomic_load_nand_64_seq_cst GPR:$addr, GPR:$incr)),
(PseudoAtomicLoadNand64 GPR:$addr, GPR:$incr, 7)>;

def : PseudoMaskedAMOPat<int_riscv_masked_atomicrmw_xchg_i64,
PseudoMaskedAtomicSwap32>;
def : PseudoMaskedAMOPat<int_riscv_masked_atomicrmw_add_i64,
PseudoMaskedAtomicLoadAdd32>;
def : PseudoMaskedAMOPat<int_riscv_masked_atomicrmw_sub_i64,
PseudoMaskedAtomicLoadSub32>;
def : PseudoMaskedAMOPat<int_riscv_masked_atomicrmw_nand_i64,
PseudoMaskedAtomicLoadNand32>;
def : PseudoMaskedAMOMinMaxPat<int_riscv_masked_atomicrmw_max_i64,
PseudoMaskedAtomicLoadMax32>;
def : PseudoMaskedAMOMinMaxPat<int_riscv_masked_atomicrmw_min_i64,
PseudoMaskedAtomicLoadMin32>;
def : PseudoMaskedAMOPat<int_riscv_masked_atomicrmw_umax_i64,
PseudoMaskedAtomicLoadUMax32>;
def : PseudoMaskedAMOPat<int_riscv_masked_atomicrmw_umin_i64,
PseudoMaskedAtomicLoadUMin32>;

/// 64-bit compare and exchange

def PseudoCmpXchg64 : PseudoCmpXchg;
defm : PseudoCmpXchgPat<"atomic_cmp_swap_64", PseudoCmpXchg64, i64>;

Expand Down Expand Up @@ -408,6 +411,7 @@ defm : AMOPat2<"atomic_load_min_32", "AMOMIN_W", i32>;
defm : AMOPat2<"atomic_load_umax_32", "AMOMAXU_W", i32>;
defm : AMOPat2<"atomic_load_umin_32", "AMOMINU_W", i32>;

let Predicates = [HasStdExtA, IsRV64] in
defm : PseudoCmpXchgPat<"atomic_cmp_swap_32", PseudoCmpXchg32, i32>;

let Predicates = [HasAtomicLdSt] in {
Expand Down