Skip to content

[AArch64] Fix missing pfalse diagnostic #77746

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 1 commit into from
Jan 11, 2024
+9 −0
Merged

[AArch64] Fix missing pfalse diagnostic #77746

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
4 changes: 4 additions & 0 deletions llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -6110,6 +6110,9 @@ bool AArch64AsmParser::showMatchError(SMLoc Loc, unsigned ErrCode,
case Match_AddSubLSLImm3ShiftLarge:
return Error(Loc,
"expected 'lsl' with optional integer in range [0, 7]");
case Match_InvalidSVEPNRasPPRPredicateBReg:
return Error(Loc,
"Expected predicate-as-counter register name with .B suffix");
default:
llvm_unreachable("unexpected error code!");
}
Expand Down Expand Up @@ -6690,6 +6693,7 @@ bool AArch64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
case Match_InvalidSVEVectorListStrided4x16:
case Match_InvalidSVEVectorListStrided4x32:
case Match_InvalidSVEVectorListStrided4x64:
case Match_InvalidSVEPNRasPPRPredicateBReg:
case Match_MSR:
case Match_MRS: {
if (ErrorInfo >= Operands.size())
Expand Down
5 changes: 5 additions & 0 deletions llvm/test/MC/AArch64/SVE/pfalse-diagnostics.s
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -15,3 +15,8 @@ pfalse pn16.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: pfalse pn16.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

pfalse pn5.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Expected predicate-as-counter register name with .B suffix
// CHECK-NEXT: pfalse pn5.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: